Kvar att göra: Resultat->attenuator->PCB, Discussion, Conclusion, Abstract, Acknoledgement, (Appendix)

kretsschemor/relay_card/fp-lib-table

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 (fp_lib_table
-  (lib (name custom_footprints)(type KiCad)(uri C:/Users/Jonatan/Documents/exjobb/kretsschemor/custom_footprints.pretty)(options "")(descr ""))
+  (lib (name custom_footprints)(type KiCad)(uri J:/Users/Jonatan/Documents/skola/exjobb/kretsschemor/custom_footprints.pretty)(options "")(descr ""))
 )

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+SYMATTR Value 50
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+SYMATTR Value 50
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+SYMATTR InstName R20
+SYMATTR Value 50
+SYMBOL current 1312 80 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I3
+SYMATTR Value 1
+SYMBOL current 2224 384 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I4
+SYMATTR Value 1
+SYMBOL bv 2432 -352 R0
+SYMATTR InstName B2
+SYMATTR Value V=20*log10(V(Vut2)/V(Vin2))
+SYMBOL res 1536 -16 R0
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+SYMATTR Value {r1_val}
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+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R22
+SYMATTR Value {r2_val}
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+SYMATTR InstName R30
+SYMATTR Value {r1_val}
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+WINDOW 3 0 56 VBottom 2
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+SYMATTR Value {r2_val}
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+SYMATTR InstName R27
+SYMATTR Value {r4_val}
+SYMBOL res 1904 -368 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R28
+SYMATTR Value {r5_val}
+SYMBOL res 2016 -352 R0
+SYMATTR InstName R29
+SYMATTR Value {r6_val}
+SYMBOL res 1776 -16 R0
+SYMATTR InstName R24
+SYMATTR Value {r4_val}
+SYMBOL res 1904 -32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R25
+SYMATTR Value {r5_val}
+SYMBOL res 2016 -16 R0
+SYMATTR InstName R26
+SYMATTR Value {r6_val}
+SYMBOL res 1776 288 R0
+SYMATTR InstName R33
+SYMATTR Value {r4_val}
+SYMBOL res 1904 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R34
+SYMATTR Value {r5_val}
+SYMBOL res 2016 288 R0
+SYMATTR InstName R35
+SYMATTR Value {r6_val}
+SYMBOL pulse3b_gen 3280 -320 R0
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+SYMBOL res 5056 -336 R0
+SYMATTR InstName R15
+SYMATTR Value 50
+SYMBOL voltage 3440 -256 R0
+WINDOW 123 24 44 Left 2
+WINDOW 39 24 72 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V3
+SYMATTR Value 1500
+SYMBOL res 3424 -352 R0
+SYMATTR InstName R36
+SYMATTR Value 50
+SYMBOL bv 5264 -336 R0
+SYMATTR InstName B3
+SYMATTR Value V=20*log10(V(Vut3)/V(Vin3))
+SYMBOL res 5056 288 R0
+SYMATTR InstName R47
+SYMATTR Value 50
+SYMBOL res 4720 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R48
+SYMATTR Value 560
+SYMBOL res 4848 288 R0
+SYMATTR InstName R49
+SYMATTR Value 56
+SYMBOL res 4672 288 R0
+SYMATTR InstName R51
+SYMATTR Value 27
+SYMBOL res 3600 400 R0
+SYMATTR InstName R52
+SYMATTR Value 82
+SYMBOL res 3600 304 R0
+SYMATTR InstName R53
+SYMATTR Value 82
+SYMBOL res 3600 496 R0
+SYMATTR InstName R54
+SYMATTR Value 82
+SYMBOL res 3680 400 R0
+SYMATTR InstName R55
+SYMATTR Value 82
+SYMBOL res 3680 304 R0
+SYMATTR InstName R56
+SYMATTR Value 82
+SYMBOL res 3680 496 R0
+SYMATTR InstName R58
+SYMATTR Value 82
+SYMBOL res 3760 400 R0
+SYMATTR InstName R59
+SYMATTR Value 82
+SYMBOL res 3760 304 R0
+SYMATTR InstName R60
+SYMATTR Value 82
+SYMBOL res 3760 496 R0
+SYMATTR InstName R61
+SYMATTR Value 82
+SYMBOL res 3840 400 R0
+SYMATTR InstName R62
+SYMATTR Value 82
+SYMBOL res 3840 304 R0
+SYMATTR InstName R63
+SYMATTR Value 82
+SYMBOL res 3840 496 R0
+SYMATTR InstName R64
+SYMATTR Value 82
+SYMBOL res 3600 592 R0
+SYMATTR InstName R65
+SYMATTR Value 82
+SYMBOL res 3680 592 R0
+SYMATTR InstName R66
+SYMATTR Value 82
+SYMBOL res 3760 592 R0
+SYMATTR InstName R67
+SYMATTR Value 82
+SYMBOL res 3840 592 R0
+SYMATTR InstName R68
+SYMATTR Value 82
+SYMBOL res 3920 400 R0
+SYMATTR InstName R69
+SYMATTR Value 82
+SYMBOL res 3920 304 R0
+SYMATTR InstName R70
+SYMATTR Value 82
+SYMBOL res 3920 496 R0
+SYMATTR InstName R71
+SYMATTR Value 82
+SYMBOL res 3920 592 R0
+SYMATTR InstName R72
+SYMATTR Value 82
+SYMBOL res 4000 400 R0
+SYMATTR InstName R73
+SYMATTR Value 82
+SYMBOL res 4000 304 R0
+SYMATTR InstName R74
+SYMATTR Value 82
+SYMBOL res 4000 496 R0
+SYMATTR InstName R76
+SYMATTR Value 82
+SYMBOL res 4000 592 R0
+SYMATTR InstName R77
+SYMATTR Value 82
+SYMBOL res 4208 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R78
+SYMATTR Value 560
+SYMBOL res 4288 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R79
+SYMATTR Value 560
+SYMBOL res 4368 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R80
+SYMATTR Value 560
+SYMBOL res 4208 352 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R81
+SYMATTR Value 560
+SYMBOL res 4288 352 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R82
+SYMATTR Value 560
+SYMBOL res 4368 352 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R83
+SYMATTR Value 560
+SYMBOL res 4208 432 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R84
+SYMATTR Value 560
+SYMBOL res 4288 432 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R85
+SYMATTR Value 560
+SYMBOL res 4368 432 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R86
+SYMATTR Value 560
+SYMBOL res 4720 848 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R88
+SYMATTR Value 560
+SYMBOL res 4848 864 R0
+SYMATTR InstName R89
+SYMATTR Value 56
+SYMBOL res 3424 848 R0
+SYMATTR InstName R90
+SYMATTR Value 50
+SYMBOL res 4672 864 R0
+SYMATTR InstName R91
+SYMATTR Value 27
+SYMBOL res 3600 976 R0
+SYMATTR InstName R92
+SYMATTR Value 82
+SYMBOL res 3600 880 R0
+SYMATTR InstName R93
+SYMATTR Value 82
+SYMBOL res 3600 1072 R0
+SYMATTR InstName R94
+SYMATTR Value 82
+SYMBOL res 3680 976 R0
+SYMATTR InstName R95
+SYMATTR Value 82
+SYMBOL res 3680 880 R0
+SYMATTR InstName R118
+SYMATTR Value 82
+SYMBOL res 3680 1072 R0
+SYMATTR InstName R119
+SYMATTR Value 82
+SYMBOL res 3760 976 R0
+SYMATTR InstName R120
+SYMATTR Value 82
+SYMBOL res 3760 880 R0
+SYMATTR InstName R121
+SYMATTR Value 82
+SYMBOL res 3760 1072 R0
+SYMATTR InstName R122
+SYMATTR Value 82
+SYMBOL res 3840 976 R0
+SYMATTR InstName R123
+SYMATTR Value 82
+SYMBOL res 3840 880 R0
+SYMATTR InstName R124
+SYMATTR Value 82
+SYMBOL res 3840 1072 R0
+SYMATTR InstName R125
+SYMATTR Value 82
+SYMBOL res 3600 1168 R0
+SYMATTR InstName R126
+SYMATTR Value 82
+SYMBOL res 3680 1168 R0
+SYMATTR InstName R127
+SYMATTR Value 82
+SYMBOL res 3760 1168 R0
+SYMATTR InstName R128
+SYMATTR Value 82
+SYMBOL res 3840 1168 R0
+SYMATTR InstName R129
+SYMATTR Value 82
+SYMBOL res 3920 976 R0
+SYMATTR InstName R130
+SYMATTR Value 82
+SYMBOL res 3920 880 R0
+SYMATTR InstName R131
+SYMATTR Value 82
+SYMBOL res 3920 1072 R0
+SYMATTR InstName R132
+SYMATTR Value 82
+SYMBOL res 3920 1168 R0
+SYMATTR InstName R133
+SYMATTR Value 82
+SYMBOL res 4000 976 R0
+SYMATTR InstName R134
+SYMATTR Value 82
+SYMBOL res 4000 880 R0
+SYMATTR InstName R135
+SYMATTR Value 82
+SYMBOL res 4000 1072 R0
+SYMATTR InstName R136
+SYMATTR Value 82
+SYMBOL res 4000 1168 R0
+SYMATTR InstName R137
+SYMATTR Value 82
+SYMBOL res 4208 848 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R138
+SYMATTR Value 560
+SYMBOL res 4288 848 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R139
+SYMATTR Value 560
+SYMBOL res 4368 848 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R140
+SYMATTR Value 560
+SYMBOL res 4208 928 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R141
+SYMATTR Value 560
+SYMBOL res 4288 928 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R142
+SYMATTR Value 560
+SYMBOL res 4368 928 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R143
+SYMATTR Value 560
+SYMBOL res 4208 1008 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R144
+SYMATTR Value 560
+SYMBOL res 4288 1008 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R145
+SYMATTR Value 560
+SYMBOL res 4368 1008 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R146
+SYMATTR Value 560
+SYMBOL current 3440 368 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I5
+SYMATTR Value 1
+SYMBOL current 5072 960 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I6
+SYMATTR Value 1
+SYMBOL resistor-non-ideal 3616 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMATTR InstName X2
+SYMBOL resistor-non-ideal 3696 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X3
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3776 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X4
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X5
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3936 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X6
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4016 -272 R0
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X7
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3616 16 R0
+SYMATTR InstName X8
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3696 16 R0
+SYMATTR InstName X9
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3776 16 R0
+SYMATTR InstName X10
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 16 R0
+SYMATTR InstName X11
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3936 16 R0
+SYMATTR InstName X12
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4016 16 R0
+SYMATTR InstName X13
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3616 -176 R0
+SYMATTR InstName X14
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3696 -176 R0
+SYMATTR InstName X15
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3776 -176 R0
+SYMATTR InstName X16
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 -176 R0
+SYMATTR InstName X17
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3936 -176 R0
+SYMATTR InstName X18
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4016 -176 R0
+SYMATTR InstName X19
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3616 -80 R0
+SYMATTR InstName X20
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3696 -80 R0
+SYMATTR InstName X21
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3776 -80 R0
+SYMATTR InstName X22
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 -80 R0
+SYMATTR InstName X23
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3936 -80 R0
+SYMATTR InstName X24
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4016 -80 R0
+SYMATTR InstName X25
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4272 -368 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X26
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4272 -288 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X27
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4272 -208 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X28
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4352 -368 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X29
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4352 -288 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X30
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4352 -208 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X31
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4432 -368 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X32
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4432 -288 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X33
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4432 -208 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X34
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4640 -272 R180
+WINDOW 39 8 -15 Invisible 2
+SYMATTR SpiceLine R=56, L={ESL}, C={EPC}
+SYMATTR InstName X35
+SYMBOL resistor-non-ideal 4688 -272 R180
+WINDOW 39 8 -15 Invisible 2
+SYMATTR SpiceLine R=56, L={ESL}, C={EPC}
+SYMATTR InstName X36
+SYMBOL resistor-non-ideal 4784 -368 R90
+WINDOW 0 -5 8 VBottom 2
+WINDOW 39 5 8 VTop 2
+SYMATTR InstName X37
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4864 -272 R180
+WINDOW 39 8 -15 Left 2
+SYMATTR SpiceLine R=56, L={ESL}, C={EPC}
+SYMATTR InstName X38
+SYMBOL cap 4064 0 R0
+SYMATTR InstName C1
+SYMATTR Value {CCOMP}
+SYMBOL cap 4064 -96 R0
+SYMATTR InstName C2
+SYMATTR Value {CCOMP}
+SYMBOL cap 4064 -192 R0
+SYMATTR InstName C3
+SYMATTR Value {CCOMP}
+SYMBOL cap 4064 -288 R0
+SYMATTR InstName C4
+SYMATTR Value {CCOMP}
+SYMBOL cap 4752 -256 R180
+WINDOW 0 -37 34 Left 2
+WINDOW 3 24 8 Left 2
+SYMATTR InstName C8
+SYMATTR Value {CCOMP3}
+TEXT -200 -88 Left 2 ;In-Impedans
+TEXT 528 176 Left 2 ;Ut-Impedans
+TEXT 32 -592 Left 2 !* Första länken\n.param R1_val = 56\n.param R2_val = 560\n.param R3_val = 56
+TEXT -72 -1056 Left 2 !* Sumulation\n;.tran 0 1.0001m 1m\n;.op\n.ac dec 100 1 10G
+TEXT 1408 -96 Left 2 ;In-Impedans
+TEXT 2144 208 Left 2 ;Ut-Impedans
+TEXT 1680 -584 Left 2 !* Andra länken\n.param R4_val = 27\n.param R5_val = 560\n.param R6_val = 56
+TEXT 3752 -560 Left 5 ;Färdig dämpare för 50 Ohm -54dB
+TEXT 2984 -280 Left 2 !* Pulse config\n.param Ri=50\n.param Us=1500\n.param Ua=0
+TEXT -88 -1120 Left 5 ;Simulation command
+TEXT 5184 -432 Left 4 ;Förstärkning i dB
+TEXT 4312 -488 Left 2 ;560 Ohm
+TEXT 4288 192 Left 2 ;560 Ohm
+TEXT 4288 768 Left 2 ;560 Ohm
+TEXT 3472 208 Left 2 ;In-Impedans
+TEXT 4912 792 Left 2 ;Ut-Impedans
+TEXT 4120 -64 Left 2 ;56 Ohm
+TEXT 4640 -168 Left 2 ;28 Ohm
+TEXT 3592 -448 Left 2 ;Dämparens komponenter
+TEXT 3072 -32 Left 2 !.param ESL=1n\n.param EPC=1p
+TEXT 4304 -48 Left 2 !;.step param C_comp 10p 70p 5p
+TEXT 3080 64 Left 2 !; Compensation capacitors\n.param CCOMP=110p\n.param CCOMP3 10p
+RECTANGLE Normal 512 -944 -112 -1152 2
+RECTANGLE Normal 3584 128 4944 -464 2

ltspice/attenuator/non-ideal/attenuator 54db.asc

@@ -8,7 +8,8 @@ WIRE 2032 -384 2000 -384
 WIRE 2224 -384 2032 -384
 WIRE 2576 -384 2432 -384
 WIRE 3376 -368 3280 -368
-WIRE 3824 -368 3376 -368
+WIRE 3440 -368 3376 -368
+WIRE 3824 -368 3440 -368
 WIRE 4176 -368 3824 -368
 WIRE 4224 -368 4176 -368
 WIRE 4528 -368 4464 -368
@@ -28,6 +29,7 @@ WIRE 1776 -336 1776 -384
 WIRE 2032 -336 2032 -384
 WIRE 2224 -336 2224 -384
 WIRE 2432 -336 2432 -384
+WIRE 3440 -336 3440 -368
 WIRE 3696 -336 3616 -336
 WIRE 3776 -336 3696 -336
 WIRE 3824 -336 3824 -368
@@ -36,7 +38,6 @@ WIRE 3856 -336 3824 -336
 WIRE 3936 -336 3856 -336
 WIRE 4016 -336 3936 -336
 WIRE 4080 -336 4016 -336
-WIRE 3280 -320 3280 -368
 WIRE 4688 -320 4688 -368
 WIRE 4688 -320 4640 -320
 WIRE 4736 -320 4688 -320
@@ -57,13 +58,21 @@ WIRE 816 -288 816 -336
 WIRE 4080 -288 4080 -336
 WIRE 4176 -288 4176 -368
 WIRE 4224 -288 4176 -288
+WIRE 4304 -288 4304 -368
+WIRE 4384 -288 4384 -368
 WIRE 4528 -288 4528 -368
 WIRE 4528 -288 4464 -288
 WIRE 1312 -256 1312 -272
 WIRE 3440 -240 3440 -256
-WIRE 4688 -240 4688 -256
 WIRE 4688 -240 4640 -240
+WIRE 4736 -240 4736 -256
 WIRE 4736 -240 4688 -240
+WIRE 3696 -224 3616 -224
+WIRE 3776 -224 3696 -224
+WIRE 3856 -224 3776 -224
+WIRE 3936 -224 3856 -224
+WIRE 4016 -224 3936 -224
+WIRE 4080 -224 4016 -224
 WIRE -304 -208 -304 -224
 WIRE 1552 -208 1552 -256
 WIRE 1776 -208 1776 -256
@@ -78,6 +87,8 @@ WIRE 3936 -208 3936 -224
 WIRE 4016 -208 4016 -224
 WIRE 4176 -208 4176 -288
 WIRE 4224 -208 4176 -208
+WIRE 4304 -208 4304 -288
+WIRE 4384 -208 4384 -288
 WIRE 4528 -208 4528 -288
 WIRE 4528 -208 4464 -208
 WIRE 4688 -208 4688 -240
@@ -92,6 +103,12 @@ WIRE 608 -160 608 -208
 WIRE 816 -160 816 -208
 WIRE 1312 -160 1312 -176
 WIRE 3440 -128 3440 -160
+WIRE 3696 -128 3616 -128
+WIRE 3776 -128 3696 -128
+WIRE 3856 -128 3776 -128
+WIRE 3936 -128 3856 -128
+WIRE 4016 -128 3936 -128
+WIRE 4080 -128 4016 -128
 WIRE -304 -112 -304 -128
 WIRE 3616 -112 3616 -128
 WIRE 3696 -112 3696 -128
@@ -110,6 +127,12 @@ WIRE 1792 -48 1664 -48
 WIRE 1920 -48 1792 -48
 WIRE 2032 -48 2000 -48
 WIRE 2224 -48 2032 -48
+WIRE 3696 -32 3616 -32
+WIRE 3776 -32 3696 -32
+WIRE 3856 -32 3776 -32
+WIRE 3936 -32 3856 -32
+WIRE 4016 -32 3936 -32
+WIRE 4080 -32 4016 -32
 WIRE 3616 -16 3616 -32
 WIRE 3696 -16 3696 -32
 WIRE 3776 -16 3776 -32
@@ -378,12 +401,10 @@ DATAFLAG 1472 -48 ""
 DATAFLAG 2224 256 ""
 DATAFLAG 2496 -384 ""
 DATAFLAG 2112 -384 ""
-DATAFLAG 3552 -368 ""
-DATAFLAG 4624 -368 ""
-DATAFLAG 4928 -368 ""
 DATAFLAG 5328 -368 ""
 DATAFLAG 3536 256 ""
 DATAFLAG 4992 832 ""
+DATAFLAG 5008 -384 ""
 SYMBOL res 48 -304 R0
 SYMATTR InstName R1
 SYMATTR Value {r1_val}
@@ -837,161 +858,216 @@ WINDOW 123 0 0 Left 0
 WINDOW 39 0 0 Left 0
 SYMATTR InstName I6
 SYMATTR Value 1
-SYMBOL _JonatansLib\\resistor-non-ideal 3616 -272 R0
+SYMBOL resistor-non-ideal 3616 -272 R0
+WINDOW 39 -10 6 Invisible 0
+WINDOW 0 8 6 Left 2
+SYMATTR SpiceLine R=82, L={ESL}, C={EPC}, LC={LC}
 SYMATTR InstName X2
+SYMBOL resistor-non-ideal 3696 -272 R0
+WINDOW 39 -10 6 Invisible 0
+WINDOW 0 8 6 Left 2
 SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3696 -272 R0
 SYMATTR InstName X3
+SYMBOL resistor-non-ideal 3776 -272 R0
+WINDOW 39 -10 6 Invisible 0
+WINDOW 0 8 6 Left 2
 SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3776 -272 R0
 SYMATTR InstName X4
+SYMBOL resistor-non-ideal 3856 -272 R0
+WINDOW 39 -10 6 Invisible 0
+WINDOW 0 8 6 Left 2
 SYMATTR SpiceLine R=82, L={ESL}, C={EPC}
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 SYMATTR InstName X5
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 SYMATTR Value {CCOMP}
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 SYMATTR Value {CCOMP}
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 SYMATTR Value {CCOMP}
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 TEXT 528 176 Left 2 ;Ut-Impedans
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-TEXT -72 -1056 Left 2 !* Sumulation\n;.tran 0 1.0001m 1m\n.op\n;.ac dec 100 1 10G
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 TEXT 1408 -96 Left 2 ;In-Impedans
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@@ -999,16 +1075,16 @@ TEXT 3752 -560 Left 5 ;F
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-TEXT 4288 192 Left 2 ;560 Ohm
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 TEXT 4288 768 Left 2 ;560 Ohm
 TEXT 3472 208 Left 2 ;In-Impedans
 TEXT 4912 792 Left 2 ;Ut-Impedans
-TEXT 4120 -64 Left 2 ;56 Ohm
-TEXT 4640 -168 Left 2 ;28 Ohm
-TEXT 3592 -448 Left 2 ;Dämparens komponenter
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-TEXT 4304 -48 Left 2 !;.step param C_comp 10p 70p 5p
-TEXT 3080 64 Left 2 !; Compensation capacitors\n.param CCOMP=110p\n.param CCOMP3 10p
+TEXT 3792 -400 Left 2 ;56 Ohm
+TEXT 4640 -416 Left 2 ;28 Ohm
+TEXT 3592 -448 Left 2 ;Attenuator, 50 Ohm, 54dB
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+TEXT 5080 184 Left 2 !;.step param CCOMP 10p 300p 20p
+TEXT 4280 0 Left 2 !; Compensation capacitors\n.param CCOMP=130p\n.param CCOMP3 10p
 RECTANGLE Normal 512 -944 -112 -1152 2
 RECTANGLE Normal 3584 128 4944 -464 2

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+DATAFLAG 608 -48 ""
+DATAFLAG -144 -48 ""
+DATAFLAG 608 224 ""
+DATAFLAG -144 224 ""
+DATAFLAG 880 -336 ""
+DATAFLAG 1776 -384 ""
+DATAFLAG 1472 -384 ""
+DATAFLAG 1472 -48 ""
+DATAFLAG 2224 256 ""
+DATAFLAG 2496 -384 ""
+DATAFLAG 2112 -384 ""
+DATAFLAG 3552 320 ""
+DATAFLAG 4816 1008 ""
+DATAFLAG 5072 -368 ""
+DATAFLAG 3920 -416 ""
+DATAFLAG 4144 -416 ""
+DATAFLAG 4032 -416 ""
+SYMBOL res 48 -304 R0
+SYMATTR InstName R1
+SYMATTR Value {r1_val}
+SYMBOL res 80 -320 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R2
+SYMATTR Value {r2_val}
+SYMBOL res 192 -304 R0
+SYMATTR InstName R3
+SYMATTR Value {r3_val}
+SYMBOL res 592 -304 R0
+SYMATTR InstName R4
+SYMATTR Value 50
+SYMBOL voltage -304 -224 R0
+WINDOW 123 24 44 Left 2
+WINDOW 39 24 72 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V1
+SYMATTR Value 1500
+SYMBOL res -320 -320 R0
+SYMATTR InstName R7
+SYMATTR Value 50
+SYMBOL res 592 -16 R0
+SYMATTR InstName R11
+SYMATTR Value 50
+SYMBOL res -320 240 R0
+SYMATTR InstName R19
+SYMATTR Value 50
+SYMBOL current -304 80 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I1
+SYMATTR Value 1
+SYMBOL current 608 352 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I2
+SYMATTR Value 1
+SYMBOL res 48 -16 R0
+SYMATTR InstName R5
+SYMATTR Value {r1_val}
+SYMBOL res 80 -32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R6
+SYMATTR Value {r2_val}
+SYMBOL res 192 -16 R0
+SYMATTR InstName R8
+SYMATTR Value {r3_val}
+SYMBOL res 48 256 R0
+SYMATTR InstName R9
+SYMATTR Value {r1_val}
+SYMBOL res 80 240 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R10
+SYMATTR Value {r2_val}
+SYMBOL res 192 256 R0
+SYMATTR InstName R12
+SYMATTR Value {r3_val}
+SYMBOL bv 816 -304 R0
+SYMATTR InstName B1
+SYMATTR Value V=20*log10(V(Vut)/V(Vin))
+SYMBOL res 1536 -352 R0
+SYMATTR InstName R13
+SYMATTR Value {r1_val}
+SYMBOL res 1568 -368 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R14
+SYMATTR Value {r2_val}
+SYMBOL res 2208 -352 R0
+SYMATTR InstName R16
+SYMATTR Value 50
+SYMBOL voltage 1312 -272 R0
+WINDOW 123 24 44 Left 2
+WINDOW 39 24 72 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V2
+SYMATTR Value 1500
+SYMBOL res 1296 -368 R0
+SYMATTR InstName R17
+SYMATTR Value 50
+SYMBOL res 2208 -16 R0
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+SYMATTR Value 50
+SYMBOL res 1296 272 R0
+SYMATTR InstName R20
+SYMATTR Value 50
+SYMBOL current 1312 80 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I3
+SYMATTR Value 1
+SYMBOL current 2224 384 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I4
+SYMATTR Value 1
+SYMBOL bv 2432 -352 R0
+SYMATTR InstName B2
+SYMATTR Value V=20*log10(V(Vut2)/V(Vin2))
+SYMBOL res 1536 -16 R0
+SYMATTR InstName R21
+SYMATTR Value {r1_val}
+SYMBOL res 1568 -32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R22
+SYMATTR Value {r2_val}
+SYMBOL res 1536 288 R0
+SYMATTR InstName R30
+SYMATTR Value {r1_val}
+SYMBOL res 1568 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R31
+SYMATTR Value {r2_val}
+SYMBOL res 1760 -352 R0
+SYMATTR InstName R27
+SYMATTR Value {r4_val}
+SYMBOL res 1904 -368 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R28
+SYMATTR Value {r5_val}
+SYMBOL res 2016 -352 R0
+SYMATTR InstName R29
+SYMATTR Value {r6_val}
+SYMBOL res 1776 -16 R0
+SYMATTR InstName R24
+SYMATTR Value {r4_val}
+SYMBOL res 1904 -32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R25
+SYMATTR Value {r5_val}
+SYMBOL res 2016 -16 R0
+SYMATTR InstName R26
+SYMATTR Value {r6_val}
+SYMBOL res 1776 288 R0
+SYMATTR InstName R33
+SYMATTR Value {r4_val}
+SYMBOL res 1904 272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R34
+SYMATTR Value {r5_val}
+SYMBOL res 2016 288 R0
+SYMATTR InstName R35
+SYMATTR Value {r6_val}
+SYMBOL pulse3b_gen 3280 -320 R0
+SYMATTR InstName X1
+SYMBOL res 4800 -336 R0
+SYMATTR InstName R15
+SYMATTR Value 50
+SYMBOL res 4464 -352 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R23
+SYMATTR Value 560
+SYMBOL res 4592 -336 R0
+SYMATTR InstName R32
+SYMATTR Value 56
+SYMBOL voltage 3440 -256 R0
+WINDOW 123 24 44 Left 2
+WINDOW 39 24 72 Left 2
+SYMATTR Value2 AC 1
+SYMATTR InstName V3
+SYMATTR Value 1500
+SYMBOL res 3424 -352 R0
+SYMATTR InstName R36
+SYMATTR Value 50
+SYMBOL res 4416 -336 R0
+SYMATTR InstName R37
+SYMATTR Value 47
+SYMBOL res 4800 352 R0
+SYMATTR InstName R54
+SYMATTR Value 50
+SYMBOL res 4464 336 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R55
+SYMATTR Value 560
+SYMBOL res 4592 352 R0
+SYMATTR InstName R56
+SYMATTR Value 56
+SYMBOL res 4416 352 R0
+SYMATTR InstName R58
+SYMATTR Value 47
+SYMBOL res 3616 384 R0
+SYMATTR InstName R59
+SYMATTR Value 820
+SYMBOL res 3712 384 R0
+SYMATTR InstName R60
+SYMATTR Value 1500
+SYMBOL res 3616 496 R0
+SYMATTR InstName R61
+SYMATTR Value 820
+SYMBOL res 3712 496 R0
+SYMATTR InstName R62
+SYMATTR Value 1200
+SYMBOL res 3616 608 R0
+SYMATTR InstName R63
+SYMATTR Value 820
+SYMBOL res 3712 608 R0
+SYMATTR InstName R64
+SYMATTR Value 1200
+SYMBOL res 3616 720 R0
+SYMATTR InstName R65
+SYMATTR Value 820
+SYMBOL res 3712 720 R0
+SYMATTR InstName R66
+SYMATTR Value 1200
+SYMBOL res 3808 384 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R67
+SYMATTR Value 820
+SYMBOL res 3808 288 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R68
+SYMATTR Value 1500
+SYMBOL res 3920 384 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R69
+SYMATTR Value 820
+SYMBOL res 3920 288 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R70
+SYMATTR Value 1200
+SYMBOL res 4032 384 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R71
+SYMATTR Value 820
+SYMBOL res 4032 288 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R72
+SYMATTR Value 1200
+SYMBOL res 4144 384 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R73
+SYMATTR Value 820
+SYMBOL res 4144 288 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R74
+SYMATTR Value 1200
+SYMBOL res 4464 1024 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R76
+SYMATTR Value 560
+SYMBOL res 4592 1040 R0
+SYMATTR InstName R77
+SYMATTR Value 56
+SYMBOL res 3424 1024 R0
+SYMATTR InstName R78
+SYMATTR Value 50
+SYMBOL res 4416 1040 R0
+SYMATTR InstName R79
+SYMATTR Value 47
+SYMBOL res 3616 1072 R0
+SYMATTR InstName R80
+SYMATTR Value 820
+SYMBOL res 3712 1072 R0
+SYMATTR InstName R81
+SYMATTR Value 1500
+SYMBOL res 3616 1184 R0
+SYMATTR InstName R82
+SYMATTR Value 820
+SYMBOL res 3712 1184 R0
+SYMATTR InstName R83
+SYMATTR Value 1200
+SYMBOL res 3616 1296 R0
+SYMATTR InstName R84
+SYMATTR Value 820
+SYMBOL res 3712 1296 R0
+SYMATTR InstName R85
+SYMATTR Value 1200
+SYMBOL res 3616 1408 R0
+SYMATTR InstName R86
+SYMATTR Value 820
+SYMBOL res 3712 1408 R0
+SYMATTR InstName R87
+SYMATTR Value 1200
+SYMBOL res 3808 1072 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R88
+SYMATTR Value 820
+SYMBOL res 3808 976 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R89
+SYMATTR Value 1500
+SYMBOL res 3920 1072 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R90
+SYMATTR Value 820
+SYMBOL res 3920 976 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R91
+SYMATTR Value 1200
+SYMBOL res 4032 1072 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R92
+SYMATTR Value 820
+SYMBOL res 4032 976 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R93
+SYMATTR Value 1200
+SYMBOL res 4144 1072 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R94
+SYMATTR Value 820
+SYMBOL res 4144 976 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName R95
+SYMATTR Value 1200
+SYMBOL current 3440 432 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I5
+SYMATTR Value 1
+SYMBOL current 4816 1136 R180
+WINDOW 0 24 80 Left 2
+WINDOW 3 24 0 Left 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName I6
+SYMATTR Value 1
+SYMBOL bv 5008 -336 R0
+SYMATTR InstName B3
+SYMATTR Value V=20*log10(V(Vut3)/V(Vin3))
+SYMBOL resistor-non-ideal 3632 -256 R0
+SYMATTR InstName X3
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3632 -144 R0
+SYMATTR InstName X4
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3632 -32 R0
+SYMATTR InstName X5
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3632 80 R0
+SYMATTR InstName X6
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3728 -256 R0
+SYMATTR InstName X7
+SYMATTR SpiceLine R=1500, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3728 -144 R0
+SYMATTR InstName X8
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3728 -32 R0
+SYMATTR InstName X9
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3728 80 R0
+SYMATTR InstName X10
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 -320 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 Invisible 2
+SYMATTR InstName X11
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3968 -320 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 Invisible 2
+SYMATTR InstName X12
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4080 -320 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X13
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4192 -320 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X14
+SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3856 -416 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X15
+SYMATTR SpiceLine R=1500, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 3968 -416 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X16
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4080 -416 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X17
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4192 -416 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 VBottom 2
+SYMATTR InstName X18
+SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL cap 3776 48 R0
+WINDOW 3 24 56 Left 0
+SYMATTR Value {CCOMP}
+SYMATTR InstName C1
+SYMBOL cap 3776 -64 R0
+WINDOW 3 24 56 Left 0
+SYMATTR Value {CCOMP}
+SYMATTR InstName C2
+SYMBOL cap 3776 -160 R0
+WINDOW 3 24 56 Left 0
+SYMATTR Value {CCOMP}
+SYMATTR InstName C3
+SYMBOL cap 3776 -272 R0
+WINDOW 3 24 56 Left 0
+SYMATTR Value {CCOMP}
+SYMATTR InstName C4
+TEXT -200 -88 Left 2 ;In-Impedans
+TEXT 528 176 Left 2 ;Ut-Impedans
+TEXT 32 -592 Left 2 !* Första länken\n;.param R1_val = 1992\n;.param R2_val = 1992\n;.param R3_val = 820
+TEXT 1408 -96 Left 2 ;In-Impedans
+TEXT 2144 208 Left 2 ;Ut-Impedans
+TEXT 1680 -584 Left 2 !* Andra länken\n.param R4_val = 47\n.param R5_val = 560\n.param R6_val = 56
+TEXT 3752 -560 Left 5 ;Färdig dämpare för 1000 Ohm -60dB
+TEXT 3432 680 Left 2 ;Typ 1992 Ohm
+TEXT 3936 448 Left 2 ;Typ 1992 Ohm
+TEXT 3432 1368 Left 2 ;Typ 1992 Ohm
+TEXT 3936 1136 Left 2 ;Typ 1992 Ohm
+TEXT 2984 -280 Left 2 !* Pulse config\n.param Ri=50\n.param Us=1500\n.param Ua=0
+TEXT -88 -1120 Left 5 ;Simulation command
+TEXT 5008 -448 Left 4 ;Förstärkning i dB
+TEXT 3464 280 Left 2 ;In-Impedans
+TEXT 4744 968 Left 2 ;Ut-Impedans
+TEXT 3600 -496 Left 2 ;Dämparens komponenter
+TEXT 4088 -112 Left 2 !.param ESL=.1n\n.param EPC=1p\n.param LC=1n
+TEXT 3816 -40 Left 2 ;Typ 1992 Ohm
+TEXT 4008 -232 Left 2 ;Typ 1992 Ohm
+TEXT -80 -1064 Left 2 !* Simulation\n;.tran 0 1000.5u 1m\n;.op\n.ac dec 100 1 10G
+TEXT -248 -600 Left 2 !* Första länken\n.param R1_val = 1009\n.param R2_val = 111803\n.param R3_val = 50
+TEXT 4088 8 Left 2 !; Compensation capacitors\n.param CCOMP=80p
+TEXT 4864 24 Left 2 !;.step param CCOMP 1p 300p 20p
+RECTANGLE Normal 512 -944 -112 -1152 2
+RECTANGLE Normal 4704 208 3584 -512 2

ltspice/attenuator/non-ideal/attenuator 60db.asc

@@ -1,5 +1,5 @@
 Version 4
-SHEET 1 5764 1572
+SHEET 1 5764 1652
 WIRE 3824 -416 3808 -416
 WIRE 3920 -416 3904 -416
 WIRE 3936 -416 3920 -416
@@ -16,7 +16,8 @@ WIRE 2032 -384 2000 -384
 WIRE 2224 -384 2032 -384
 WIRE 2576 -384 2432 -384
 WIRE 3376 -368 3280 -368
-WIRE 3680 -368 3376 -368
+WIRE 3440 -368 3376 -368
+WIRE 3680 -368 3440 -368
 WIRE 3808 -368 3808 -416
 WIRE 3808 -368 3680 -368
 WIRE 4256 -368 4256 -416
@@ -36,7 +37,9 @@ WIRE 1776 -336 1776 -384
 WIRE 2032 -336 2032 -384
 WIRE 2224 -336 2224 -384
 WIRE 2432 -336 2432 -384
-WIRE 3280 -320 3280 -368
+WIRE 3440 -336 3440 -368
+WIRE 4432 -336 4432 -368
+WIRE 4432 -336 4352 -336
 WIRE 3808 -320 3808 -368
 WIRE 3824 -320 3808 -320
 WIRE 3920 -320 3920 -416
@@ -50,7 +53,8 @@ WIRE 4144 -320 4128 -320
 WIRE 4160 -320 4144 -320
 WIRE 4256 -320 4256 -368
 WIRE 4256 -320 4240 -320
-WIRE 4432 -320 4432 -368
+WIRE 4352 -320 4352 -336
+WIRE 4432 -320 4432 -336
 WIRE 4608 -320 4608 -368
 WIRE 4816 -320 4816 -368
 WIRE 5008 -320 5008 -368
@@ -58,14 +62,18 @@ WIRE -304 -304 -304 -336
 WIRE 3680 -304 3680 -368
 WIRE 3680 -304 3632 -304
 WIRE 3728 -304 3680 -304
+WIRE 3792 -304 3728 -304
 WIRE 64 -288 64 -336
 WIRE 208 -288 208 -336
 WIRE 608 -288 608 -336
 WIRE 816 -288 816 -336
 WIRE 3632 -288 3632 -304
 WIRE 3728 -288 3728 -304
+WIRE 3792 -272 3792 -304
 WIRE 1312 -256 1312 -272
 WIRE 3440 -240 3440 -256
+WIRE 4352 -240 4352 -256
+WIRE 4432 -240 4352 -240
 WIRE -304 -208 -304 -224
 WIRE 1552 -208 1552 -256
 WIRE 1776 -208 1776 -256
@@ -76,6 +84,8 @@ WIRE 4432 -208 4432 -240
 WIRE 3632 -192 3632 -208
 WIRE 3728 -192 3728 -208
 WIRE 3728 -192 3632 -192
+WIRE 3792 -192 3792 -208
+WIRE 3792 -192 3728 -192
 WIRE 4608 -192 4608 -240
 WIRE 4816 -192 4816 -240
 WIRE 5008 -192 5008 -240
@@ -87,13 +97,17 @@ WIRE 208 -160 208 -208
 WIRE 608 -160 608 -208
 WIRE 816 -160 816 -208
 WIRE 1312 -160 1312 -176
+WIRE 3792 -160 3792 -192
 WIRE 3440 -128 3440 -160
 WIRE -304 -112 -304 -128
 WIRE 3632 -80 3632 -96
 WIRE 3728 -80 3728 -96
 WIRE 3728 -80 3632 -80
+WIRE 3792 -80 3792 -96
+WIRE 3792 -80 3728 -80
 WIRE 3632 -64 3632 -80
 WIRE 3728 -64 3728 -80
+WIRE 3792 -64 3792 -80
 WIRE 64 -48 -304 -48
 WIRE 96 -48 64 -48
 WIRE 208 -48 176 -48
@@ -116,8 +130,11 @@ WIRE 2224 0 2224 -48
 WIRE 3632 32 3632 16
 WIRE 3728 32 3728 16
 WIRE 3728 32 3632 32
+WIRE 3792 32 3792 0
+WIRE 3792 32 3728 32
 WIRE 3632 48 3632 32
 WIRE 3728 48 3728 32
+WIRE 3792 48 3792 32
 WIRE -304 96 -304 80
 WIRE 1312 96 1312 80
 WIRE 64 128 64 80
@@ -131,7 +148,9 @@ WIRE 3632 144 3632 128
 WIRE 3680 144 3632 144
 WIRE 3728 144 3728 128
 WIRE 3728 144 3680 144
-WIRE 3680 176 3680 144
+WIRE 3792 144 3792 112
+WIRE 3792 144 3728 144
+WIRE 3680 208 3680 144
 WIRE 64 224 -304 224
 WIRE 96 224 64 224
 WIRE 208 224 176 224
@@ -146,144 +165,144 @@ WIRE 2224 256 2032 256
 WIRE 64 272 64 224
 WIRE 208 272 208 224
 WIRE 608 272 608 224
-WIRE 3824 272 3808 272
-WIRE 3920 272 3904 272
-WIRE 3936 272 3920 272
-WIRE 4032 272 4016 272
-WIRE 4048 272 4032 272
-WIRE 4144 272 4128 272
-WIRE 4160 272 4144 272
-WIRE 4256 272 4240 272
 WIRE 1312 288 1312 256
 WIRE 1552 304 1552 256
 WIRE 1792 304 1792 256
 WIRE 2032 304 2032 256
 WIRE 2224 304 2224 256
-WIRE 3680 320 3440 320
-WIRE 3808 320 3808 272
-WIRE 3808 320 3680 320
-WIRE 4256 320 4256 272
-WIRE 4432 320 4256 320
-WIRE 4480 320 4432 320
-WIRE 4608 320 4560 320
-WIRE 4816 320 4608 320
-WIRE 3440 352 3440 320
+WIRE 3824 352 3808 352
+WIRE 3920 352 3904 352
+WIRE 3936 352 3920 352
+WIRE 4032 352 4016 352
+WIRE 4048 352 4032 352
+WIRE 4144 352 4128 352
+WIRE 4160 352 4144 352
+WIRE 4256 352 4240 352
 WIRE -304 368 -304 336
-WIRE 3808 368 3808 320
-WIRE 3824 368 3808 368
-WIRE 3920 368 3920 272
-WIRE 3920 368 3904 368
-WIRE 3936 368 3920 368
-WIRE 4032 368 4032 272
-WIRE 4032 368 4016 368
-WIRE 4048 368 4032 368
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-WIRE 4144 368 4128 368
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-WIRE 4256 368 4256 320
-WIRE 4256 368 4240 368
-WIRE 4432 368 4432 320
-WIRE 4608 368 4608 320
-WIRE 4816 368 4816 320
-WIRE 3680 384 3680 320
-WIRE 3680 384 3632 384
-WIRE 3728 384 3680 384
 WIRE 64 400 64 352
 WIRE 208 400 208 352
 WIRE 608 400 608 352
 WIRE 1312 400 1312 368
-WIRE 3632 400 3632 384
-WIRE 3728 400 3728 384
+WIRE 3680 400 3440 400
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+WIRE 3808 400 3680 400
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 WIRE 1552 432 1552 384
 WIRE 1792 432 1792 384
 WIRE 2032 432 2032 384
 WIRE 2224 432 2224 384
-WIRE 3440 480 3440 432
-WIRE 4432 480 4432 448
-WIRE 3632 496 3632 480
-WIRE 3728 496 3728 480
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-WIRE 4048 960 4032 960
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-WIRE 4816 1008 4608 1008
-WIRE 3440 1040 3440 1008
-WIRE 3808 1056 3808 1008
-WIRE 3824 1056 3808 1056
-WIRE 3920 1056 3920 960
-WIRE 3920 1056 3904 1056
-WIRE 3936 1056 3920 1056
-WIRE 4032 1056 4032 960
-WIRE 4032 1056 4016 1056
-WIRE 4048 1056 4032 1056
-WIRE 4144 1056 4144 960
-WIRE 4144 1056 4128 1056
-WIRE 4160 1056 4144 1056
-WIRE 4256 1056 4256 1008
-WIRE 4256 1056 4240 1056
-WIRE 4432 1056 4432 1008
-WIRE 4608 1056 4608 1008
-WIRE 4816 1056 4816 1008
-WIRE 3680 1072 3680 1008
-WIRE 3680 1072 3632 1072
-WIRE 3728 1072 3680 1072
-WIRE 3632 1088 3632 1072
-WIRE 3728 1088 3728 1072
-WIRE 3440 1168 3440 1120
-WIRE 4432 1168 4432 1136
-WIRE 3632 1184 3632 1168
-WIRE 3728 1184 3728 1168
-WIRE 3728 1184 3632 1184
-WIRE 4608 1184 4608 1136
-WIRE 4816 1184 4816 1136
-WIRE 3632 1200 3632 1184
-WIRE 3728 1200 3728 1184
-WIRE 3632 1296 3632 1280
-WIRE 3728 1296 3728 1280
-WIRE 3728 1296 3632 1296
-WIRE 3632 1312 3632 1296
-WIRE 3728 1312 3728 1296
-WIRE 3632 1408 3632 1392
-WIRE 3728 1408 3728 1392
-WIRE 3728 1408 3632 1408
-WIRE 3632 1424 3632 1408
-WIRE 3728 1424 3728 1408
-WIRE 3632 1520 3632 1504
-WIRE 3680 1520 3632 1520
-WIRE 3728 1520 3728 1504
-WIRE 3728 1520 3680 1520
-WIRE 3680 1552 3680 1520
+WIRE 3440 432 3440 400
+WIRE 3808 448 3808 400
+WIRE 3824 448 3808 448
+WIRE 3920 448 3920 352
+WIRE 3920 448 3904 448
+WIRE 3936 448 3920 448
+WIRE 4032 448 4032 352
+WIRE 4032 448 4016 448
+WIRE 4048 448 4032 448
+WIRE 4144 448 4144 352
+WIRE 4144 448 4128 448
+WIRE 4160 448 4144 448
+WIRE 4256 448 4256 400
+WIRE 4256 448 4240 448
+WIRE 4432 448 4432 400
+WIRE 4608 448 4608 400
+WIRE 4816 448 4816 400
+WIRE 3680 464 3680 400
+WIRE 3680 464 3632 464
+WIRE 3728 464 3680 464
+WIRE 3632 480 3632 464
+WIRE 3728 480 3728 464
+WIRE 3440 560 3440 512
+WIRE 4432 560 4432 528
+WIRE 3632 576 3632 560
+WIRE 3728 576 3728 560
+WIRE 3728 576 3632 576
+WIRE 4608 576 4608 528
+WIRE 4816 576 4816 528
+WIRE 3632 592 3632 576
+WIRE 3728 592 3728 576
+WIRE 3632 688 3632 672
+WIRE 3728 688 3728 672
+WIRE 3728 688 3632 688
+WIRE 3632 704 3632 688
+WIRE 3728 704 3728 688
+WIRE 3632 800 3632 784
+WIRE 3728 800 3728 784
+WIRE 3728 800 3632 800
+WIRE 3632 816 3632 800
+WIRE 3728 816 3728 800
+WIRE 3632 912 3632 896
+WIRE 3680 912 3632 912
+WIRE 3728 912 3728 896
+WIRE 3728 912 3680 912
+WIRE 3680 944 3680 912
+WIRE 3824 1040 3808 1040
+WIRE 3920 1040 3904 1040
+WIRE 3936 1040 3920 1040
+WIRE 4032 1040 4016 1040
+WIRE 4048 1040 4032 1040
+WIRE 4144 1040 4128 1040
+WIRE 4160 1040 4144 1040
+WIRE 4256 1040 4240 1040
+WIRE 3680 1088 3440 1088
+WIRE 3808 1088 3808 1040
+WIRE 3808 1088 3680 1088
+WIRE 4256 1088 4256 1040
+WIRE 4432 1088 4256 1088
+WIRE 4480 1088 4432 1088
+WIRE 4608 1088 4560 1088
+WIRE 4816 1088 4608 1088
+WIRE 3440 1120 3440 1088
+WIRE 3808 1136 3808 1088
+WIRE 3824 1136 3808 1136
+WIRE 3920 1136 3920 1040
+WIRE 3920 1136 3904 1136
+WIRE 3936 1136 3920 1136
+WIRE 4032 1136 4032 1040
+WIRE 4032 1136 4016 1136
+WIRE 4048 1136 4032 1136
+WIRE 4144 1136 4144 1040
+WIRE 4144 1136 4128 1136
+WIRE 4160 1136 4144 1136
+WIRE 4256 1136 4256 1088
+WIRE 4256 1136 4240 1136
+WIRE 4432 1136 4432 1088
+WIRE 4608 1136 4608 1088
+WIRE 4816 1136 4816 1088
+WIRE 3680 1152 3680 1088
+WIRE 3680 1152 3632 1152
+WIRE 3728 1152 3680 1152
+WIRE 3632 1168 3632 1152
+WIRE 3728 1168 3728 1152
+WIRE 3440 1248 3440 1200
+WIRE 4432 1248 4432 1216
+WIRE 3632 1264 3632 1248
+WIRE 3728 1264 3728 1248
+WIRE 3728 1264 3632 1264
+WIRE 4608 1264 4608 1216
+WIRE 4816 1264 4816 1216
+WIRE 3632 1280 3632 1264
+WIRE 3728 1280 3728 1264
+WIRE 3632 1376 3632 1360
+WIRE 3728 1376 3728 1360
+WIRE 3728 1376 3632 1376
+WIRE 3632 1392 3632 1376
+WIRE 3728 1392 3728 1376
+WIRE 3632 1488 3632 1472
+WIRE 3728 1488 3728 1472
+WIRE 3728 1488 3632 1488
+WIRE 3632 1504 3632 1488
+WIRE 3728 1504 3728 1488
+WIRE 3632 1600 3632 1584
+WIRE 3680 1600 3632 1600
+WIRE 3728 1600 3728 1584
+WIRE 3728 1600 3680 1600
+WIRE 3680 1632 3680 1600
 FLAG 208 -160 0
 FLAG 64 -160 0
 FLAG 608 -160 0
@@ -321,18 +340,18 @@ FLAG 4816 -192 0
 FLAG 3440 -128 0
 FLAG 4608 -192 0
 FLAG 3280 -176 0
-FLAG 3680 176 0
+FLAG 3680 208 0
 FLAG 4432 -208 0
-FLAG 4816 496 0
-FLAG 3440 480 0
-FLAG 4608 496 0
-FLAG 3680 864 0
-FLAG 4432 480 0
-FLAG 4816 1184 0
-FLAG 3440 1168 0
-FLAG 4608 1184 0
-FLAG 3680 1552 0
-FLAG 4432 1168 0
+FLAG 4816 576 0
+FLAG 3440 560 0
+FLAG 4608 576 0
+FLAG 3680 944 0
+FLAG 4432 560 0
+FLAG 4816 1264 0
+FLAG 3440 1248 0
+FLAG 4608 1264 0
+FLAG 3680 1632 0
+FLAG 4432 1248 0
 FLAG 3376 -368 Vin3
 FLAG 4816 -368 Vut3
 FLAG 5008 -192 0
@@ -349,18 +368,9 @@ DATAFLAG 1472 -48 ""
 DATAFLAG 2224 256 ""
 DATAFLAG 2496 -384 ""
 DATAFLAG 2112 -384 ""
-DATAFLAG 3552 -368 ""
-DATAFLAG 4352 -368 ""
-DATAFLAG 4672 -368 ""
-DATAFLAG 3552 320 ""
-DATAFLAG 4816 1008 ""
+DATAFLAG 3552 400 ""
+DATAFLAG 4816 1088 ""
 DATAFLAG 5072 -368 ""
-DATAFLAG 3728 -192 ""
-DATAFLAG 3728 32 ""
-DATAFLAG 3728 -80 ""
-DATAFLAG 3920 -416 ""
-DATAFLAG 4144 -416 ""
-DATAFLAG 4032 -416 ""
 SYMBOL res 48 -304 R0
 SYMATTR InstName R1
 SYMATTR Value {r1_val}
@@ -522,18 +532,11 @@ SYMBOL res 2016 288 R0
 SYMATTR InstName R35
 SYMATTR Value {r6_val}
 SYMBOL pulse3b_gen 3280 -320 R0
+WINDOW 0 8 6 Left 2
 SYMATTR InstName X1
 SYMBOL res 4800 -336 R0
 SYMATTR InstName R15
 SYMATTR Value 50
-SYMBOL res 4464 -352 R270
-WINDOW 0 32 56 VTop 2
-WINDOW 3 0 56 VBottom 2
-SYMATTR InstName R23
-SYMATTR Value 560
-SYMBOL res 4592 -336 R0
-SYMATTR InstName R32
-SYMATTR Value 56
 SYMBOL voltage 3440 -256 R0
 WINDOW 123 24 44 Left 2
 WINDOW 39 24 72 Left 2
@@ -543,173 +546,170 @@ SYMATTR Value 1500
 SYMBOL res 3424 -352 R0
 SYMATTR InstName R36
 SYMATTR Value 50
-SYMBOL res 4416 -336 R0
-SYMATTR InstName R37
-SYMATTR Value 47
-SYMBOL res 4800 352 R0
+SYMBOL res 4800 432 R0
 SYMATTR InstName R54
 SYMATTR Value 50
-SYMBOL res 4464 336 R270
+SYMBOL res 4464 416 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R55
 SYMATTR Value 560
-SYMBOL res 4592 352 R0
+SYMBOL res 4592 432 R0
 SYMATTR InstName R56
 SYMATTR Value 56
-SYMBOL res 4416 352 R0
+SYMBOL res 4416 432 R0
 SYMATTR InstName R58
 SYMATTR Value 47
-SYMBOL res 3616 384 R0
+SYMBOL res 3616 464 R0
 SYMATTR InstName R59
 SYMATTR Value 820
-SYMBOL res 3712 384 R0
+SYMBOL res 3712 464 R0
 SYMATTR InstName R60
 SYMATTR Value 1500
-SYMBOL res 3616 496 R0
+SYMBOL res 3616 576 R0
 SYMATTR InstName R61
 SYMATTR Value 820
-SYMBOL res 3712 496 R0
+SYMBOL res 3712 576 R0
 SYMATTR InstName R62
 SYMATTR Value 1200
-SYMBOL res 3616 608 R0
+SYMBOL res 3616 688 R0
 SYMATTR InstName R63
 SYMATTR Value 820
-SYMBOL res 3712 608 R0
+SYMBOL res 3712 688 R0
 SYMATTR InstName R64
 SYMATTR Value 1200
-SYMBOL res 3616 720 R0
+SYMBOL res 3616 800 R0
 SYMATTR InstName R65
 SYMATTR Value 820
-SYMBOL res 3712 720 R0
+SYMBOL res 3712 800 R0
 SYMATTR InstName R66
 SYMATTR Value 1200
-SYMBOL res 3808 384 R270
+SYMBOL res 3808 464 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R67
 SYMATTR Value 820
-SYMBOL res 3808 288 R270
+SYMBOL res 3808 368 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R68
 SYMATTR Value 1500
-SYMBOL res 3920 384 R270
+SYMBOL res 3920 464 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R69
 SYMATTR Value 820
-SYMBOL res 3920 288 R270
+SYMBOL res 3920 368 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R70
 SYMATTR Value 1200
-SYMBOL res 4032 384 R270
+SYMBOL res 4032 464 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R71
 SYMATTR Value 820
-SYMBOL res 4032 288 R270
+SYMBOL res 4032 368 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R72
 SYMATTR Value 1200
-SYMBOL res 4144 384 R270
+SYMBOL res 4144 464 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R73
 SYMATTR Value 820
-SYMBOL res 4144 288 R270
+SYMBOL res 4144 368 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R74
 SYMATTR Value 1200
-SYMBOL res 4464 1024 R270
+SYMBOL res 4464 1104 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R76
 SYMATTR Value 560
-SYMBOL res 4592 1040 R0
+SYMBOL res 4592 1120 R0
 SYMATTR InstName R77
 SYMATTR Value 56
-SYMBOL res 3424 1024 R0
+SYMBOL res 3424 1104 R0
 SYMATTR InstName R78
 SYMATTR Value 50
-SYMBOL res 4416 1040 R0
+SYMBOL res 4416 1120 R0
 SYMATTR InstName R79
 SYMATTR Value 47
-SYMBOL res 3616 1072 R0
+SYMBOL res 3616 1152 R0
 SYMATTR InstName R80
 SYMATTR Value 820
-SYMBOL res 3712 1072 R0
+SYMBOL res 3712 1152 R0
 SYMATTR InstName R81
 SYMATTR Value 1500
-SYMBOL res 3616 1184 R0
+SYMBOL res 3616 1264 R0
 SYMATTR InstName R82
 SYMATTR Value 820
-SYMBOL res 3712 1184 R0
+SYMBOL res 3712 1264 R0
 SYMATTR InstName R83
 SYMATTR Value 1200
-SYMBOL res 3616 1296 R0
+SYMBOL res 3616 1376 R0
 SYMATTR InstName R84
 SYMATTR Value 820
-SYMBOL res 3712 1296 R0
+SYMBOL res 3712 1376 R0
 SYMATTR InstName R85
 SYMATTR Value 1200
-SYMBOL res 3616 1408 R0
+SYMBOL res 3616 1488 R0
 SYMATTR InstName R86
 SYMATTR Value 820
-SYMBOL res 3712 1408 R0
+SYMBOL res 3712 1488 R0
 SYMATTR InstName R87
 SYMATTR Value 1200
-SYMBOL res 3808 1072 R270
+SYMBOL res 3808 1152 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R88
 SYMATTR Value 820
-SYMBOL res 3808 976 R270
+SYMBOL res 3808 1056 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R89
 SYMATTR Value 1500
-SYMBOL res 3920 1072 R270
+SYMBOL res 3920 1152 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R90
 SYMATTR Value 820
-SYMBOL res 3920 976 R270
+SYMBOL res 3920 1056 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R91
 SYMATTR Value 1200
-SYMBOL res 4032 1072 R270
+SYMBOL res 4032 1152 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R92
 SYMATTR Value 820
-SYMBOL res 4032 976 R270
+SYMBOL res 4032 1056 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R93
 SYMATTR Value 1200
-SYMBOL res 4144 1072 R270
+SYMBOL res 4144 1152 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R94
 SYMATTR Value 820
-SYMBOL res 4144 976 R270
+SYMBOL res 4144 1056 R270
 WINDOW 0 32 56 VTop 2
 WINDOW 3 0 56 VBottom 2
 SYMATTR InstName R95
 SYMATTR Value 1200
-SYMBOL current 3440 432 R180
+SYMBOL current 3440 512 R180
 WINDOW 0 24 80 Left 2
 WINDOW 3 24 0 Left 2
 WINDOW 123 0 0 Left 0
 WINDOW 39 0 0 Left 0
 SYMATTR InstName I5
 SYMATTR Value 1
-SYMBOL current 4816 1136 R180
+SYMBOL current 4816 1216 R180
 WINDOW 0 24 80 Left 2
 WINDOW 3 24 0 Left 2
 WINDOW 123 0 0 Left 0
@@ -719,91 +719,144 @@ SYMATTR Value 1
 SYMBOL bv 5008 -336 R0
 SYMATTR InstName B3
 SYMATTR Value V=20*log10(V(Vut3)/V(Vin3))
-SYMBOL _JonatansLib\\resistor-non-ideal 3632 -256 R0
+SYMBOL resistor-non-ideal 3632 -256 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X3
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3632 -144 R0
+SYMBOL resistor-non-ideal 3632 -144 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X4
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3632 -32 R0
+SYMBOL resistor-non-ideal 3632 -32 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X5
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3632 80 R0
+SYMBOL resistor-non-ideal 3632 80 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X6
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3728 -256 R0
+SYMBOL resistor-non-ideal 3728 -256 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X7
 SYMATTR SpiceLine R=1500, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3728 -144 R0
+SYMBOL resistor-non-ideal 3728 -144 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X8
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3728 -32 R0
+SYMBOL resistor-non-ideal 3728 -32 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X9
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3728 80 R0
+SYMBOL resistor-non-ideal 3728 80 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
 SYMATTR InstName X10
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3856 -320 R270
+SYMBOL resistor-non-ideal 3856 -320 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -23 8 Invisible 2
 SYMATTR InstName X11
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3968 -320 R270
+SYMBOL resistor-non-ideal 3968 -320 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X12
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 4080 -320 R270
+SYMBOL resistor-non-ideal 4080 -320 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X13
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 4192 -320 R270
+SYMBOL resistor-non-ideal 4192 -320 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X14
 SYMATTR SpiceLine R=820, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3856 -416 R270
+SYMBOL resistor-non-ideal 3856 -416 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X15
 SYMATTR SpiceLine R=1500, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 3968 -416 R270
+SYMBOL resistor-non-ideal 3968 -416 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X16
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 4080 -416 R270
+SYMBOL resistor-non-ideal 4080 -416 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X17
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
-SYMBOL _JonatansLib\\resistor-non-ideal 4192 -416 R270
+SYMBOL resistor-non-ideal 4192 -416 R270
 WINDOW 0 5 8 VTop 2
-WINDOW 39 -5 8 VBottom 2
+WINDOW 39 -5 8 Invisible 2
 SYMATTR InstName X18
 SYMATTR SpiceLine R=1200, L={ESL}, C={EPC}
+SYMBOL cap 3776 48 R0
+WINDOW 3 24 56 Left 1
+SYMATTR Value {CCOMP}
+SYMATTR InstName C1
+SYMBOL cap 3776 -64 R0
+WINDOW 3 24 56 Left 1
+SYMATTR Value {CCOMP}
+SYMATTR InstName C2
+SYMBOL cap 3776 -160 R0
+WINDOW 3 24 56 Left 1
+SYMATTR Value {CCOMP}
+SYMATTR InstName C3
+SYMBOL cap 3776 -272 R0
+WINDOW 3 24 56 Left 1
+SYMATTR Value {CCOMP}
+SYMATTR InstName C4
+SYMBOL resistor-non-ideal 4432 -272 R180
+WINDOW 0 -55 8 Left 2
+WINDOW 39 8 -15 Invisible 2
+SYMATTR InstName X19
+SYMATTR SpiceLine R=47, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4512 -368 R270
+WINDOW 0 5 8 VTop 2
+WINDOW 39 -5 8 Invisible 2
+SYMATTR InstName X20
+SYMATTR SpiceLine R=560, L={ESL}, C={EPC}
+SYMBOL resistor-non-ideal 4608 -288 R0
+WINDOW 0 8 6 Left 2
+WINDOW 39 -10 6 Invisible 0
+SYMATTR InstName X21
+SYMATTR SpiceLine R=56, L={ESL}, C={EPC}
+SYMBOL cap 4336 -320 R0
+WINDOW 3 -72 66 Left 1
+SYMATTR Value {CCOMP3}
+SYMATTR InstName C5
 TEXT -200 -88 Left 2 ;In-Impedans
 TEXT 528 176 Left 2 ;Ut-Impedans
 TEXT 32 -592 Left 2 !* Första länken\n;.param R1_val = 1992\n;.param R2_val = 1992\n;.param R3_val = 820
 TEXT 1408 -96 Left 2 ;In-Impedans
 TEXT 2144 208 Left 2 ;Ut-Impedans
 TEXT 1680 -584 Left 2 !* Andra länken\n.param R4_val = 47\n.param R5_val = 560\n.param R6_val = 56
-TEXT 3752 -560 Left 5 ;Färdig dämpare för 1000 Ohm -60dB
-TEXT 3432 680 Left 2 ;Typ 1992 Ohm
-TEXT 3936 448 Left 2 ;Typ 1992 Ohm
-TEXT 3432 1368 Left 2 ;Typ 1992 Ohm
-TEXT 3936 1136 Left 2 ;Typ 1992 Ohm
+TEXT 3736 -576 Left 5 ;Färdig dämpare för 1000 Ohm -60dB
+TEXT 3432 760 Left 2 ;Typ 1992 Ohm
+TEXT 3936 528 Left 2 ;Typ 1992 Ohm
+TEXT 3432 1448 Left 2 ;Typ 1992 Ohm
+TEXT 3936 1216 Left 2 ;Typ 1992 Ohm
 TEXT 2984 -280 Left 2 !* Pulse config\n.param Ri=50\n.param Us=1500\n.param Ua=0
 TEXT -88 -1120 Left 5 ;Simulation command
 TEXT 5008 -448 Left 4 ;Förstärkning i dB
-TEXT 3464 280 Left 2 ;In-Impedans
-TEXT 4744 968 Left 2 ;Ut-Impedans
-TEXT 3600 -496 Left 2 ;Dämparens komponenter
-TEXT 3304 -32 Left 2 !.param ESL=1n\n.param EPC=1p
-TEXT 3816 -40 Left 2 ;Typ 1992 Ohm
-TEXT 4008 -232 Left 2 ;Typ 1992 Ohm
-TEXT -80 -1064 Left 2 !* Simulation\n;.tran 0 1000.5u 1m\n.op\n;.ac dec 100 1 10G
+TEXT 3464 360 Left 2 ;In-Impedans
+TEXT 4744 1048 Left 2 ;Ut-Impedans
+TEXT 4088 -112 Left 2 !.param ESL=.1n\n.param EPC=1p\n.param LC=1n
+TEXT 3624 -392 Left 2 ;1992 Ohm
+TEXT 3976 -456 Left 2 ;1992 Ohm
+TEXT -80 -1064 Left 2 !* Simulation\n;.tran 0 1000.5u 1m\n;.op\n.ac dec 100 1 10G
 TEXT -248 -600 Left 2 !* Första länken\n.param R1_val = 1009\n.param R2_val = 111803\n.param R3_val = 50
+TEXT 4784 88 Left 2 !;.step param CCOMP 20p 100p 10p\n;.step param CCOMP3 1p 60p 5p
+TEXT 3592 -496 Left 2 ;Attenuator, 1000 Ohm, 61dB
+TEXT 4088 0 Left 2 !; Compensation capacitors\n.param CCOMP=40p\n.param CCOMP3=30p
 RECTANGLE Normal 512 -944 -112 -1152 2
-RECTANGLE Normal 4704 208 3584 -512 2
+RECTANGLE Normal 4704 176 3584 -512 2

rapport/abstract.tex

@@ -1,3 +1,4 @@
+
 %%% Abstract.tex --- 
 %% 
 %% Filename: Abstract.tex
@@ -31,6 +32,8 @@
 %%% Code:
 % !TeX root = main.tex
 
+\todo[Gör en abstract!]
+
 If your thesis is written in English, the primary abstract would go here while the Swedish abstract would be optional.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

rapport/acknowledgments.tex

@@ -32,8 +32,10 @@
 
 \swedishenglish{\chapter*{Författarens tack}}{\chapter*{Acknowledgments}}
 
+\todo[Gör en acknoledgements]
 \texttt{Acknowledgments.tex}
 
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 %%% Acknowledgments.tex<2> ends here
 

rapport/conclusion.tex

@@ -33,7 +33,6 @@
 
 \chapter{Conclusion}
 \label{cha:conclusion}
-This chapter concludes the project and suggests future work.
 
 %%%%%%%%%%%%%%%%%%%%%%%
 \squareit{
@@ -46,6 +45,9 @@ and practitioners) must also be described.
 
 Besvara frågeställningen}
 
+The main goal of this thesis was to examine the potential of resusing old test equipment with newer standards and how to assure that the results are reliable. A method to verify the test equipment according to the latest standard was suggested in this thesis and some considerations for automating this procedure was made.
+
+\todo[Lägg in fin lista med svar på research questions här]
 
 %%%%%%%%%%%%%%%%%%%%%%%
 \section{Future work}

rapport/discussion.tex

@@ -32,8 +32,11 @@
 
 % !TeX root = main.tex
 \chapter{Discussion}\label{cha:discussion}
+\todo[skriv nåt bra i det här kapitlet]
+This chapter 
 
 \section{Results}
+
 \section{Initial measurement of the performance of the old equipment}
 
 As can be seen in \autoref{tab:initial_measurements} and \autoref{tab:initial_measurements_cna}, some values exceeded the limits (marked in red). Three of these values even exceeds the old standard's limits, thus indicating that the equipment should probably be usable with the new standard after some service or calibration. With this in mind, the course of the project will be targeted towards the design of an automated verification system, as described in \autoref{sec:planning}. With such a verification equipment at hand, the calibration of the generators might be easier to perform as well.

rapport/intro.tex

@@ -45,7 +45,7 @@ An appealing alternative would be the possibility to reuse the test equipment th
 
 \section{Aim}
 
-The main goal of this work is to investigate the potential of reusing test equipment, made for a previous version of a standard, with the current version of that standard and how to assure that the test results are reliable.
+The main goal of this work is to investigate the possibility of reusing test equipment, made for a previous version of a standard, with the current version of that standard and how to assure that the test results are reliable.
 
 If the above goal is met, the verification process of the system is desired to be automated.
 
@@ -53,11 +53,13 @@ If the above goal is met, the verification process of the system is desired to b
 
 The following questions will be answered in this paper:
 
-\begin{itemize}
+\todo[Lägg in lista med easylist istället https://anorien.csc.warwick.ac.uk/mirrors/CTAN/macros/latex/contrib/easylist/easylist-doc.pdf]
+
+\begin{enumerate}
     \item{Can test equipment made for ISO 7637-2:2004, be used for testing compliance against ISO 7637-2:2011, the newer version of the standard?}
     \item{If it can; What considerations must be made to allow for automating the test and verification process?}
     \item{If it can't; What causes the failure, and what possible fixes can be made to make the equipment usable for the newer standard?}
-\end{itemize}
+\end{enumerate}
 
 \section{Delimitations}
 This paper only compares the standard ISO 7637\nd2:2004 to ISO 7637\nd2:2011 and ISO~16750\nd2:2012, because these are the most recent versions of the standards.
@@ -85,8 +87,15 @@ This paper only considers the test equipment for ISO~7637-2 that was available a
 \end{table}
 
 \section{Report structure}
+The theory chapter presents all necessary theory to back up the methods used in the project.
+
+The method chapter describes how the project was executed so that it can be replicated.
+
+The result chapter is tightly coupled to the method chapter, in such a way that each header can be found in both. This allows for an easy correlation between the method and its result.
+
+The discussion chapter reflects on the results achieved and comments on the methods used. This is also where source critisism is brought up.
 
-\todo[fyll i upplägg när det väl är klart]
+The conclusion chapter reconnects the project to the original research questions. There are also some suggestions for topics that need further research related to the project.
 
 %\nocite{scigen}
 %We have included Paper \ref{art:scigen}

rapport/main.tex

@@ -40,6 +40,8 @@
 %\usepackage[]{xcolor}
 %\newwatermark[allpages,color=red!10,angle=45,scale=2,xpos=0,ypos=-80]{DRAFT}
 %\newwatermark[allpages,color=red!10,angle=45,scale=2,xpos=0,ypos=80]{DRAFT}
+% Alternative that works
+\usepackage{draftwatermark}
 
 %%% Define command for playing around with margin paragraphs.
 \definecolor{Warning}{rgb}{1.0,0.5,0.0}

rapport/method.tex

@@ -180,14 +180,14 @@ Three different dummy loads are needed. One \SI{2}{\ohm} load for load dump A an
 %%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Components}
 \label{sec:dummy_load:components}
-At first the momentary worst case powers and voltages were calculated by hand, using \autoref{eq:dummy_load_peak}. But to find components that can handle these momentary powers proved very difficult, and it is not necessary since the pulse power is only high for a very short time. 
+At first the momentary worst case powers and voltages were calculated by hand, using \autoref{eq:dummy_load_peak}. But to find components that withstand these high momentary powers proved very difficult, and it is not necessary since the pulse power is only high for a very short time. 
 
 \begin{equation}
     P_{peak} = \left( \frac{U_S}{R_S+R_L} \right)^2 R_L
     \label{eq:dummy_load_peak}
 \end{equation}
 
-Instead of selecting components based on peak power they can be selected based on energy over time. Although, not all manufacturers specify this data in the datasheet. To get the proper values for this project, a simulation was made with LTSpice. The LTSpice circuit can be seen in \autoref{fig:ltspice-pulse-energy}. There are preconstructed models for all of the relevant pulses, but the parameters are not tweakable. Thus, the pulse offset is removed, the magnitude is normalized and then multiplied by the desired $U_S$ using the behavioural voltage source. The power dissipated in the dummy load is then integrated over time to achieve the energy. The circuit translates to the calculation shown in \autoref{eq:dummy_load_energy}.
+Instead of selecting components based on peak power they can be selected based on energy over time. Although, not all manufacturers specify this data in the datasheet. To get the proper values for this project, a simulation was made with LTSpice. The simulated circuit can be seen in \autoref{fig:ltspice-pulse-energy}. There are preconstructed models for all of the relevant pulses, but the parameters are not tweakable. Thus, the pulse offset is removed, the magnitude is normalized and then multiplied by the desired $U_S$ using the behavioural voltage source. The power dissipated in the dummy load is then integrated over time to achieve the energy. The simulated circuit translates to the calculation shown in \autoref{eq:dummy_load_energy}.
 
 \begin{equation}
     E_{dummy load} = \int_{t_0}^{t_1}P(t)dt
@@ -215,28 +215,45 @@ Both the circuit schematic and layout editing of the board were performed in the
 
 Before ordering the PCB, it was printed in 1:1 scale and attached to a piece of card board. The card board was then populated with the components already at hand to ensure that the footprints are correct and that the placement of the components makes sense and does not collide.
 
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Measurements}
 When the dummy loads had been assembled, their resistances were determined using four wire resistance measurement directly at the PCB's connection points, as described in \autoref{sec:measurement:resistance}.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \section{Design of the switching fixture and the embedded attenuators}
-The chosen implementation requires a fixture that switches and attenuators, which purpose is to switch the pulse to the desired attenuator or to the dummy load. It must be able to handle the momentary pulse energies and voltages and should not distort the pulse.
+The chosen implementation requires a fixture with switches and attenuators, which purpose is to multiplex the pulse to the desired attenuator or to the dummy load. The principle is shown in \autoref{fig:relay_box}.
+
+\begin{figure}[h]
+    \captionsetup{width=.5\linewidth}
+    \centering
+    \includegraphics[width=0.5\textwidth]{relay_box}
+    \caption{The multiplexing relay box can couple each of the three inputs through any of the attenuators. It can also connect the external dummy load to the + and - signal.}
+    \label{fig:relay_box}
+\end{figure}
+
+Only Pulse 3a and Pulse 3b were considered when designing these attenuators, since all other test pulses will be coupled to the separate dummy load. The attenuators must be able to withstand the pulse energies and voltages and should not distort the pulses. Preferably, the attenuators should also be able to withstand the worst case settings in the pulse generator with regard to voltage and power.
+
+%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Components}
+The same methods were used for the attenuators as for the dummy loads to determine the number of resistors needed to share the power and voltage.
 
-Only Pulse 3a and Pulse 3b were considered when designing these attenuators, since all other test pulses will be coupled to the separate dummy load.
+The relays were chosen based on high breakdown voltage between open contacts.
 
 %%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Attenuators}
-The target attenuation was decided to mimic the commercial attenuators, described in \autoref{sec:hv-attenuators}, where the \SI{50}{\ohm} attenuator has an attenuation of \SI{54.7}{\deci\bel} and the \SI{1000}{\ohm} attenuator has an attenuation of \SI{60.1}{\deci\bel}.
+The target attenuation was decided to mimic the commercial attenuators, introduced in \autoref{sec:hv-attenuators}, where the \SI{50}{\ohm} attenuator has an attenuation of \SI{54.7}{\deci\bel} and the \SI{1000}{\ohm} attenuator has an attenuation of \SI{60.1}{\deci\bel}.
 
 The two attenuators were implemented as $\Pi$-attenuators. The values for the attenuators were retrieved from an online calculator\footnote{$\Pi$ attenuator calculator \url{https://chemandy.com/calculators/matching-pi-attenuator-calculator.htm}}, and then simulated in LTSpice to verify the values.
 
 By dividing the attenuators into two $\Pi$-networks, the series resistance required is lower compared to realizing them in a single $\Pi$-link. This is desirable because the parasitic capacitance, which is dependent of the resistor package and not the resistance value, will influence a high value resistor at lower frequencies than it would on a low value resistor, as explained in \autoref{sec:theory:resistors_at_high_frequencies}.
 
-When the ideal resistor values had been achieved, the energy over time and maximum voltage for each resistor was retrieved by simulation in the same way as for the dummy load described in \autoref{sec:dummy_load:components}. Based on this, the minimum number of discrete resistors needed to withstand the pulse energy was calculated. In the same way the minimum number of series resistors to withstand the maximum pulse voltage was calculated.
+When the ideal resistor values had been achieved, the power over time and maximum voltage for each resistor was retrieved by simulation in a similar way as for the dummy load described in \autoref{sec:dummy_load:components}. Based on this, the minimum number of discrete resistors needed to withstand the pulse energy was calculated. The minimum number of series resistors to withstand the maximum pulse voltage was also retrived from the simulation.
 
 With the minimum number of discrete resistors needed for each ideal resistor known, a constellation of available resistor values was constructed to approximate the nominal value with as few resistors as possible.
 
-When the number of resistors and their constellations was decided, all of the discrete ideal resistors were replaced with non-ideal models in the simulation software. Then the attenuators were checked in frequency domain, as well as how the pulses were affected in time domain.
+When the number of resistors and their constellations was decided, all of the discrete ideal resistors were replaced with non-ideal models in the simulation software. Each lead inductance was set to \SI{1}{\nano\henry}, the internal inductance was set to \SI{0.1}{\nano\henry} and the internal capacitance was set to \SI{1}{\pico\farad}. Then the attenuators were checked in frequency domain, as well as how the pulses were affected in time domain. If the required \SI{400}{\mega\hertz} bandwidth could not be achieved, frequency compensation with capacitors was attempted.
 
 %%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{PCB}
@@ -249,9 +266,17 @@ The measurement connectors accessible on the outside of the encapsulation must s
 
 The EDA tool has functionality for design rule checking, DRC, but there are some limitations in this function that inhibit its use in this case. The DRC in KiCad only allows to set the clearance for a specified net to all other nets. In this case it is only desired to restrict the clearance between the high voltage traces to the traces that must be considered safe. It is allowed for one high voltage trace to be close to another high voltage trace, it is only the functional isolation requirement of \SI{3}{\milli\meter} that applies here. The output signal and the output ground can also be close to each other, since both are considered safe.
 
-The high voltage traces was placed on the top layer of the PCB, while all signal traces were placed on the bottom layer. To aid the design process without the DRC, a workaround was used to ensure that that enough clearance was kept between the pads and the traces. The \SI{6}{\milli\meter} clearance was added to the package footprint as a ring on a user layer in the EDA, as seen in \autoref{fig:kicad_footprint}. This is not an enforced rule, but it helps during the manual design process.
+The high voltage traces were placed on the top layer of the PCB, while all signal traces were placed on the bottom layer. To aid the design process without the DRC, a workaround was used to ensure that that enough clearance was kept between the pads and the traces. The \SI{6}{\milli\meter} clearance was added to the package footprint as a graphical circle on a user layer in the EDA, as seen in \autoref{fig:relay_footprint}. This is not an enforced rule, but it helps during the manual design process.
+
+\begin{figure}[h]
+    \captionsetup{width=.5\linewidth}
+    \centering
+    \includegraphics[width=0.5\textwidth]{relay_footprint}
+    \caption{Decorational circles were made on the relay footprint to mark the creepage and clearance distance required.}
+    \label{fig:relay_footprint}
+\end{figure}
 
-Before the PCB was sent for manufacturing, it was also printed in 1:1 scale as the dummy load PCB described in \autoref{sec:dummy_load_pcb}. This also helps to ensure the critical positioning of the \SI{4}{\mm} banana connectors that will attach to the test equipment, as seen in \autoref{fig:relay_card_card_board_equipment}.
+The layout was printed in 1:1 scale to verify the layout in the same way as for the dummy load. This was especially important due to the critical positioning of the \SI{4}{\mm} banana connectors that will attach to the test equipment.
 
 When the PCB was delivered, it was visually inspected before assembling. Some modifications were required to fulfill the clearance criteria, these were made using a rotary multitool to machine away the undesired part of the traces.
 
@@ -259,13 +284,62 @@ When the PCB was delivered, it was visually inspected before assembling. Some mo
 \subsection{Measurements}
 Since the relay card will be used in measuring pulses with short rise times, it is of importance to know that it does not distort the signal too much. It is desired to measure the magnitude response in the frequency domain, as well as the test pulse in time domain.
 
-To measure the magnitude response, an S21 measurement was performed using the ZVL network analyzer. To be able to connect the network analyzer, a fixture was made to mimic the front panel of the CNA~200. A programmable relay card was used to control the relays in the switching fixture during the test. The setup can be seen in \autoref{fig:relay_card_measurement_s21}.
+To measure the magnitude response, an S21 measurement was performed using the ZVL network analyzer. A fixture was made to mimic the front panel of the CNA~200 to allow for a representative connection of the relay card. The setup can be seen in \autoref{fig:network_analyzing}. This setup proved to be unstable at first, as moving the coaxial wires and the grounding wire greatly affected the results for the higher frequencies. Because of the unstable results early in the measuring process, a modification was made to shorten the ground connection by attaching a braid as close as the attenuator grounds as possible and then grounding it directly to the fixture case, as depicted in \autoref{fig:ground_braid}. All subsequent measurements were performed with this modification.
 
-The signal was measured for each output terminal through each of the attenuators to get the magnitude response for the intended use. To see how well the design suppresses unconnected signals, the magnitude response was also measured when the signal was disconnected completely, i.e. all the relays in the fixture were open. In addition to this, the magnitude response was also measured with all but the relays on the current terminal closed, to see if there was any overhearing on the circuit board from the other terminals and the traces after the relays. The results were saved both as an image and as raw data in the form of complex numbers in a CSV file to allow for further analysis and plotting.
+The signal was measured for each output terminal through each of the attenuators to get the magnitude response for the intended use, \autoref{fig:relay_box_other_open} shows this for the + terminal. To see how well the design suppresses unconnected signals, the magnitude response was also measured when the signal was disconnected completely, i.e. all the relays in the fixture were opened as s\autoref{fig:relay_box_all_open}. In addition to this, the magnitude response was also measured with all but the relays on the current terminal closed, seen in \autoref{fig:relay_box_other_closed}, to see if there was any overhearing on the circuit board from the other terminals and the traces after the relays. The results were saved both as an image and as raw data in the form of complex numbers in a CSV file to allow for further analysis and plotting.
 
-A single relay was also measured using the network analyzer to get a perception of its high frequency properties. The setup was made by soldering coaxial cable directly to the relay, with as short connecting wires as possible to prevent any influence on the result from the wires. The setup can be seen in \autoref{fig:relay_s21}.
+A single relay was also measured using the network analyzer to get a perception of its high frequency properties. The setup was made by soldering coaxial cable directly to the relay, with as short connecting wires as possible to prevent any influence on the result from the wires. The setup can be seen in \autoref{fig:relay-setup}.
 
 To measure the test pulses through the attenuators, the switching fixture was connected to the CNA~200 and the pulses were measured on the intended connectors using an oscilloscope, as seen in \autoref{fig:relay_card_measurement_time}. The results were saved both as an image and as data points in a CVS file, for further analysis.
 
 For comparison, the commercial attenuators were also measured in frequency domain with the ZVL and in time domain using the oscilloscope.
 
+
+\begin{figure}[H]
+	\centering
+	\begin{subfigure}[t]{0.48\textwidth}
+	    \includegraphics[width=\textwidth]{network_analyzing}
+	    \caption{The network analyzer sends its signal into the attenuator through the metallic test rig and receives it back through the BNC outlet of the attenuator.}
+	    \label{fig:network_analyzing}
+	\end{subfigure}
+	\begin{subfigure}[t]{0.48\textwidth}
+    	\includegraphics[width=\textwidth]{ground_braid}
+	    \caption{The modified grounding path.}
+	    \label{fig:ground_braid}
+	\end{subfigure}
+
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{relay_measurement}
+		\caption{The relay measured with coaxial wires.}
+		\label{fig:relay-setup}
+	\end{subfigure}
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{relay_card_measurement_time}
+		\caption{The time measurement setup. Both the commercial and the constructed attenuators were measured in this setup.}
+		\label{fig:relay_card_measurement_time}
+	\end{subfigure}
+	\caption{The test setups for frequency and time measurements of the attenuators.}
+   	\label{fig:dummy-load-pcb}
+\end{figure}
+
+
+\begin{figure}
+	\centering
+	\begin{subfigure}[t]{0.3\textwidth}
+		\includegraphics[width=\textwidth]{relay_box_other_open}
+		\caption{The intended signal through the attenuator.}
+		\label{fig:relay_box_other_open}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.3\textwidth}
+		\includegraphics[width=\textwidth]{relay_box_all_open}
+		\caption{The isolation of the signal from the cominging terminals to the output of the attenuator.}
+		\label{fig:relay_box_all_open}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.3\textwidth}
+		\includegraphics[width=\textwidth]{relay_box_other_closed}
+		\caption{The isolation of the signal from all other signal paths connected to the output of the attenuator.}
+		\label{fig:relay_box_other_closed}
+	\end{subfigure}
+	\caption{The different scenarios that were measured in frequency domain for the + terminal to the \SI{50}{\ohm} attenuator. Corresponding measurements were made for the - and the PE terminal as well as for the \SI{1000}{\ohm} attenuator.}
+\end{figure}
+

rapport/references.bib

@@ -142,7 +142,6 @@
 @techreport{iso_guidance_review,
     author= {ISO} ,
     type = {Guidance},
-    key = {ISO 7637-2:2011},
     month = mar,
     year = {2019},
     title = {Guidance on the Systematic Review processing ISO},
@@ -153,7 +152,6 @@
 @techreport{vishay_hf_resistor,
     author= {VISHAY INTERTECHNOLOGY, INC.} ,
     type = {Technical note},
-    key = {ISO 7637-2:2011},
     month = feb,
     year = {2009},
     title = {Frequency Response of Thin Film Chip Resistors},
@@ -161,6 +159,18 @@
     note = "Available at \url{https://www.vishay.com/docs/60107/freqresp.pdf}"
 }
 
+
+
+@techreport{avx_cap_parasitic,
+    author= {Jeffrey Cain, AVX} ,
+    type = {Technical note},
+    month = unknown,
+    year = {unknown},
+    title = {PARASITIC INDUCTANCE OFMULTILAYER CERAMIC CAPACITORS},
+    volume = {unknown},
+    note = "Available at \url{https://www.avx.com/docs/techinfo/CeramicCapacitors/parasitc.pdf}"
+}
+
 @Book{theCircuitDesignersCompanion,
   author = {Peter Wilson},
   title = {The circuit designer's companion},

rapport/results.tex

@@ -44,9 +44,9 @@ Since the test equipment was mostly in line with the new standards, the first pr
 \section{Comparison between the old and the new standard}
 The differences of importance between the old and new standards will be presented in this chapter to see what parameters might be a problem for the older equipment to fulfil.
 
-One of the most notable differences is the removal of a test pulse from ISO~7637\nd2 that was called \emph{Pulse 5a}. This was instead introduced to the ISO~16750\nd2 under the name \emph{Load dump A}.
+One of the most notable differences is the removal of a test pulse from ISO~7637\nd2 that was called \emph{Pulse 5a}. This was instead introduced to the ISO~16750\nd2 under the name \emph{Load~dump~A}.
 
-Only the properties that proved to differ are mentioned in the results.
+Only the properties that were found to differ are mentioned in the results.
 
 %%%%%%%%%%%%%%%%%%%%
 \subsection{Supply voltages}
@@ -237,10 +237,10 @@ The 3rd alternative was chosen because of the convenience of a fully automatic s
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%
 \section{Design of dummy loads}
+The design of the dummy loads is described in this chapter.
 
 %%%%%%%%%%%%%%%%%%
 \subsection{Components}
-
 The results of the maximum momentary power is shown in \autoref{tab:dummy_load_worst_case}. The MPG~200 can generate much higher voltage than the LD~200 which yields a higher momentary power to the dummy loads with these values.
 
 \begin{table}[h]
@@ -279,7 +279,7 @@ The maximum energy transferred to the \SI{2}{\ohm}, however, is delivered by the
    	\label{fig:dummy2_energy}
 \end{figure}
 
-The LTO100 family from Vishay was chosen because of its high power characteristics and because the maximum overload energy curve was specified in its datasheet. Whith the datasheet and simulation side by side, a worst ratio between the simulated energy and the energy specified in the datasheet was determined. The worst case found for the different pulses and dummy loads can be found in \autoref{tab:dummy_load_energies}.
+The LTO100 family\footnote{\url{https://www.vishay.com/docs/50051/lto100.pdf}} from Vishay was chosen because of its high power characteristics and because the maximum overload energy curve was specified in its datasheet. Whith the datasheet and simulation side by side, a worst ratio between the simulated energy and the energy specified in the datasheet was determined. The worst case found for the different pulses and dummy loads can be found in \autoref{tab:dummy_load_energies}.
 
 \begin{table}[h]
     \caption{The worst case ratio between the simulation energies and the datasheet specification. The ratio equals the minimum number of resistors needed to share the energy.}
@@ -313,15 +313,13 @@ When the least number of resistors required had been determined, some different
 
 Because of the high voltages present on the board, a minumum creepage of 3mm was used. This is in line with the \mbox{EN 60664-1} standard \cite{en_60664_1}. The board was perforated to allow for better air flow past the resistors, improving the cooling. The mounting holes for the card was placed in a \SI[product-units=single]{105 x 105}{\milli\meter} square, allowing a \SI{120}{\milli\meter} fan to be mounted on top of the card using mounting hardware.
 
-A two layer board was chosen, and all of the traces were mirrored on both layers to get as much conductive cross sectional area as possible, and thus lowering the resistance and power dissipation in the traces. The default copper thickness from the manufacturer\footnote{Cogra Pro AB https://www.cogra.se/produkter/monsterkort/\url{}},  was \SI{18}{\micro\meter}, but this PCB was ordered with \SI{60}{\micro\meter} thick copper layer to further extend the cross sectional areas. The width of the traces for the \SI{2}{\ohm} load was chosen as wide as possible without violating the \SI{3}{\milli\meter} creepage distance.
-
-The PCB layout was tested by printing it out and making a mockup board using a piece of card board, see \autoref{fig:dummy-load-prototype}. In this way, the resulting board was a perfect fit on the first try, as seen in \autoref{fig:dummy-load-assembled}.
+A two layer board was chosen, and all of the traces were mirrored on both layers to get as much conductive cross sectional area as possible, and thus lowering the resistance and power dissipation in the traces. The default copper thickness from the manufacturer\footnote{Cogra Pro AB \url{ https://www.cogra.se/produkter/monsterkort/}},  was \SI{18}{\micro\meter}, but this PCB was ordered with \SI{60}{\micro\meter} thick copper layer to further extend the cross sectional areas. The width of the traces for the \SI{2}{\ohm} load was chosen as wide as possible without violating the \SI{3}{\milli\meter} creepage distance.
 
 \begin{figure}[H]
 	\centering
 	\begin{subfigure}[t]{0.48\textwidth}
 	    \includegraphics[width=\textwidth]{dummy-load-prototype}
-	    \caption{Before the dummy load PCB was sent for manufacturing, it was printed and placed on a piece of card board to ensure the footprints are correct and that the placement is not obstructing anything vital.}
+	    \caption{Card board was used to test the PCB layout before it was sent to manufacture.}
 	    \label{fig:dummy-load-prototype}
 	\end{subfigure}
 	\begin{subfigure}[t]{0.48\textwidth}
@@ -353,20 +351,20 @@ When the PCB was delivered, it was visually inspected before assembling. The com
 
 %%%%%%%%%%%%%%%%%%
 \subsection{Measurements}
-The resistance at the dummy loads are presented in \autoref{tab:four-wire-result}.
+The resistance of the dummy loads are presented in \autoref{tab:four-wire-result}.
 
 \begin{table}[h]
     \captionsetup{width=.6\linewidth}
-    \caption{The measured resistance of the dummy loads, and the tolerance compared to the nominal values.}
+    \caption{The measured resistance of the dummy loads, and the error compared to the nominal values.}
 %\begin{adjustbox}{width=0.6\columnwidth,center}
     \centering
     \begin{tabular}{|l|r|r|} 
         \hline
-        Nominal (\si{\ohm}) & Measured $R$ (\si{\ohm}) & Tolerance (\si{\percent}) \\
+        Nominal (\si{\ohm}) & Measured $R$ (\si{\ohm}) & Error (\si{\percent}) \\
         \hline
         2   & $2.004$   & $+ 0.2$    \\
-        10  & $9.973$   & $  0.27 $  \\
-        50  & $49.954$  & $  0.09 $  \\
+        10  & $9.973$   & $ - 0.27 $  \\
+        50  & $49.954$  & $ - 0.09 $  \\
         \hline
     \end{tabular}
 %\end{adjustbox}
@@ -374,47 +372,116 @@ The resistance at the dummy loads are presented in \autoref{tab:four-wire-result
 \end{table}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Design of the switching fixture and embedded attenuators}
+\section{Design of the switching fixture and the embedded attenuators}
+The design of the switching fixture and its attenuators is described in this chapter.
 
-Vishay's CRCW-HP series fitted this description and were easily available. 
+%%%%%%%%%%%%%%%%%%
+\subsection{Components}
+The 1206 package from Vishay's CRCW-HP series\footnote{\url{https://datasheet.octopart.com/CRCW120682R0FKEAHP-Vishay-datasheet-8359436.pdf}} was used for the embedded attenuators. They are high pulse tolerant thick-film resistors. However, they don't specify the maximum energy vs time as the LTO100 that were used for the dummy loads, but only power and voltage limits. The maximum voltage allowed for the short duration of Pulse 3, \SI{200}{\nano\second}, is specified to \SI{700}{\volt} and the maximum power to \SI{900}{\watt}.
 
+The maximum power dissipated into the \SI{50}{\ohm} attenuator will be approximately $\frac{\SI{750}{\volt}^2}{\SI{50}{\ohm}} = \SI{11250}{\watt}$. For the \SI{1000}{\ohm} attenuator it will be approximately $\frac{\SI{1429}{\volt}^2}{\SI{1000}{\ohm}} \approx \SI{2042}{\watt}$, where \SI{1429}{\volt} is the approximate voltage that would result over a \SI{1000}{\ohm} load from a \SI{1500}{\volt} source with \SI{50}{\ohm} series resistance.
+
+The Panasonic's LF-G relays were chosen as switching elements as they have a high breakdown voltage between the open contacts and had a small form factor making them suitable for the relay box.
 
 %%%%%%%%%%%%%%%%%%
 \subsection{Attenuators}
- 
- The \SI{54.7}{\deci\bel} attenuator was divided into two \SI{27.35}{\deci\bel} $\Pi$ attenuator links. When the closest values for the resistors had been chosen, using \SI{56}{\ohm} as shunt resistors and \SI{560}{\ohm} in series, the final attenuation was \SI{53.66}{\deci\bel} for the two links according to the simulation, seen in \autoref{fig:ltspice-att-ideal-54}. The input and output resistance was 
+The \SI{54.7}{\deci\bel} attenuator was divided into two \SI{27.35}{\deci\bel} $\Pi$ attenuator links. The values obtained from the online calculator was \SI{54.48}{\ohm} as the parallel resistors and \SI{581.62}{\ohm} as the series resistor. Then the closest values for the resistors was chosen to \SI{54.67}{\ohm} as parallel resistors and \SI{560}{\ohm} as series resistors. The final attenuation was \SI{53.76}{\deci\bel} for the two links according to the simulation, as seen in \autoref{fig:ltspice-54db-attenuator}. The design was realized as seen in \autoref{fig:ltspice-54db-attenuator-comp}, based on the maximum voltages and powers. Capacitors were placed in the schematic to allow for phase compensation.
+
+Since the uncompensated circuit had its \SI{3}{\deci\bel} limit at only \SI{190}{\mega\hertz}, as seen in \autoref{fig:ltspice-54db-attenuator-freq}, the circuit had to be compensated. The results after the compensation can be seen in \autoref{fig:ltspice-54db-attenuator-freq-comp} where the new \SI{3}{\deci\bel} limit is instead at \SI{1.7}{\giga\hertz}. The values used for compensating the circuit was \SI{130}{\pico\farad} for the first parallel resistance and \SI{10}{\pico\farad} for the second parallel link as seen in \autoref{fig:ltspice-54db-attenuator-comp}.
+
+\begin{figure}[h]
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-54db-attenuator}
+		\caption{The ideal circuit simulated.}
+		\label{fig:ltspice-54db-attenuator}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-54db-attenuator-freq}
+		\caption{Frequency responce of the circuit with parasitics without compensation.}
+		\label{fig:ltspice-54db-attenuator-freq}
+	\end{subfigure}
+	
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-54db-attenuator-comp}
+		\caption{Chosen topology simulated with parasitics and compensation capacitors. The components with designator X are the non-ideal resistors depicted in \autoref{fig:nonIdealResistor}}
+		\label{fig:ltspice-54db-attenuator-comp}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-54db-attenuator-freq-comp}
+		\caption{Frequency responce of the circuit with parasitics with compensation capacitors.}
+		\label{fig:ltspice-54db-attenuator-freq-comp}
+	\end{subfigure}
+	
+	\caption{The \SI{50}{\ohm} attenuator simulated.}
+\end{figure}
 
 
-The \SI{60.1}{\deci\bel} attenuator was divided into one \SI{27.35}{\deci\bel} $\Pi$ attenuator links \SI{32.75}{\deci\bel}. When the closest values for the resistors had been chosen, using \SI{56}{\ohm} as shunt resistors and \SI{56}{\ohm} in series, the final attenuation was \SI{53.66}{\deci\bel} for the two links according to the simulation, seen in \autoref{fig:ltspice-att-ideal-54}. The input and output resistance was 
-\autoref{discussion_attenuators}
+The \SI{60.1}{\deci\bel} attenuator was divided into one \SI{27.35}{\deci\bel} $\Pi$ attenuator link, the same as used in the \SI{54.7}{\deci\bel} attenuator, preceded by a \SI{32.75}{\deci\bel} $\Pi$ link with \SI{1000}{\ohm} in-impedance. When the closest values for the resistors had been chosen, using \SI{56}{\ohm} as parallel resistors and \SI{56}{\ohm} as series resistor, the final attenuation was \SI{60.33}{\deci\bel} for the two links according to the simulation, seen in \autoref{fig:ltspice-60db-attenuator}. The attenuator was then realized as seen in \autoref{fig:ltspice-60db-attenuator-comp}, based on the maximum voltages and powers.
 
+Since the uncompensated circuit had its \SI{3}{\deci\bel} limit at only \SI{130}{\mega\hertz}, as seen in \autoref{fig:ltspice-60db-attenuator-freq}, the circuit had to be compensated. The results after the compensation can be seen in \autoref{fig:ltspice-60db-attenuator-freq-comp} where the new \SI{3}{\deci\bel} limit is instead at \SI{2.2}{\giga\hertz}. The values used for compensating the circuit was \SI{40}{\pico\farad} for the first parallel resistance and \SI{30}{\pico\farad} for the second parallel link as seen in \autoref{fig:ltspice-60db-attenuator-comp}.
+
+\begin{figure}[h]
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-60db-attenuator}
+		\caption{The ideal circuit simulated.}
+		\label{fig:ltspice-60db-attenuator}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-60db-attenuator-freq}
+		\caption{Frequency responce of the circuit with parasitics without compensation.}
+		\label{fig:ltspice-60db-attenuator-freq}
+	\end{subfigure}
+	
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-60db-attenuator-comp}
+		\caption{Chosen topology simulated with parasitics and compensation capacitors. The components with designator X are the non-ideal resistors depicted in \autoref{fig:nonIdealResistor}}
+		\label{fig:ltspice-60db-attenuator-comp}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.45\textwidth}
+		\captionsetup{width=\linewidth}
+		\centering
+		\includegraphics[width=\textwidth]{ltspice-60db-attenuator-freq-comp}
+		\caption{Frequency responce of the circuit with parasitics with compensation capacitors.}
+		\label{fig:ltspice-60db-attenuator-freq-comp}
+	\end{subfigure}
+	
+	\caption{The \SI{1000}{\ohm} attenuator simulated.}
+\end{figure}
 
 %%%%%%%%%%%%%%%%%%
 \subsection{PCB}
+\todo[Fyll i den här delen så att det liknar det ovan..]
+
 To attach the relay card fixture to the \SI{4}{\mm} banana connectors on the CNA~200, three banana plugs was designed to be screwed directly to the PCB. This makes the conductors as short as possible, and also act as mechanical fastening of the PCB to the case.
 
+\begin{figure}[h]
+    \captionsetup{width=.5\linewidth}
+    \centering
+    \includegraphics[width=0.5\textwidth]{attenuator-prototype}
+    \caption{Card board was used to test the PCB layout before it was sent to manufacture.}
+    \label{fig:attenuator-prototype}
+\end{figure}
+
 %%%%%%%%%%%%%%%%%%
 \subsection{Measurements}
 
-The network analyzer was set up for S21 according to \autoref{fig:network_analyzing}. This setup proved to be unstable at first, as moving the coaxial wires and the grounding wire greatly affected the results for the higher frequencies. Because of the unstable results early in the measuring process, a modification was made to shorten the ground connection by attaching a braid as close as the attenuator grounds as possible and then grounding it directly to the fixture case, as depicted in \autoref{fig:ground_braid}. All subsequent measurements were performed with this modification.
+The results of the magnitude response measurements can be seen for the \SI{50}{\ohm} attenuator in \autoref{fig:50-s21} and for the \SI{1}{\kilo\ohm} attenuator in \autoref{fig:1k-s21}. The PAT~50 and PAT~1000 attenuators were measured as reference and their results can be seen in \autoref{fig:pat-50} and \autoref{fig:pat-1000} respectively. The frequency response of the single relay is shown in \autoref{fig:relay-result}.
 
-The results of the magnitude response measurements can be seen for the \SI{50}{\ohm} attenuator in \autoref{fig:50-s21} and for the \SI{1}{\kilo\ohm} attenuator in \autoref{fig:1k-s21}. The PAT~50 and PAT~1000 attenuators were measured as reference and their results can be seen in \autoref{fig:pat-50} and \autoref{fig:pat-1000} respectively. One of the relays that were used was also measured in a stand-alone setup according to \autoref{fig:relay-setup}, with the results presented in \autoref{fig:relay-result}.
-
-\begin{figure}[H]
-	\centering
-	\begin{subfigure}[t]{0.48\textwidth}
-	    \includegraphics[width=\textwidth]{network_analyzing}
-	    \caption{The network analyzer sends its signal into the attenuator through the metallic test rig and receives it back through the BNC outlet of the attenuator.}
-	    \label{fig:network_analyzing}
-	\end{subfigure}
-	\begin{subfigure}[t]{0.48\textwidth}
-    	\includegraphics[width=\textwidth]{ground_braid}
-	    \caption{The modified grounding path.}
-	    \label{fig:ground_braid}
-	\end{subfigure}
-	\caption{The test setup for measuring the magnitude response in the attenuators.}
-   	\label{fig:dummy-load-pcb}
-\end{figure}
+The time measurements are shown in \autoref{fig:time-measurements}
 
 
 \begin{figure}
@@ -508,7 +575,6 @@ The results of the magnitude response measurements can be seen for the \SI{50}{\
 \end{figure}
 
 \begin{figure}
-	\centering
 	\begin{subfigure}[t]{0.4\textwidth}
 		\includegraphics[width=\textwidth]{pat50}
 		\caption{PAT 50}
@@ -520,16 +586,38 @@ The results of the magnitude response measurements can be seen for the \SI{50}{\
 		\label{fig:pat-1000}
 	\end{subfigure}
 	
-	\begin{subfigure}[t]{0.4\textwidth}
-		\includegraphics[width=\textwidth]{relay_measurement}
-		\caption{The relay measured with § leads.}
-		\label{fig:relay-setup}
-	\end{subfigure}\hfill
 	\begin{subfigure}[t]{0.4\textwidth}
 		\includegraphics[width=\textwidth]{relay_open}
 		\caption{The relay's magnitude response.}
 		\label{fig:relay-result}
 	\end{subfigure}
-	\caption{Some additional S21 measurements were made for reference.}
+	\caption{The S21 measurements on the commercial attenuators and the solo relay.}
+	
+\end{figure}
+
+\begin{figure}
+	\centering
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{bk50_time}
+		\caption{The constructed \SI{50}{\ohm} attenuator}
+		\label{fig:bk50-time}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{bk1000_time}
+		\caption{The constructed \SI{1}{\kilo\ohm} attenuator}
+		\label{fig:bk1000-time}
+	\end{subfigure}
 	
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{pat50_time}
+		\caption{PAT50}
+		\label{fig:pat-50-time}
+	\end{subfigure}\hfill
+	\begin{subfigure}[t]{0.4\textwidth}
+		\includegraphics[width=\textwidth]{pat1000_time}
+		\caption{PAT1000}
+		\label{fig:pat-1000}
+	\end{subfigure}
+	\caption{The attenuator measurements in time domain, measured with the oscilloscope.}
+	\label{fig:time-measurements}
 \end{figure}

rapport/theory.tex

@@ -281,7 +281,9 @@ The test pulses are to be verified before they are applied to the DUT. The volta
 
 The verification is to be conducted with $U_A$ set to 0. There is, however, a proposal to set $U_A$ equal to the nominal voltage during the verification process, as the behaviour of the pulse generators has proven differ in this case \cite{iso_7637_5}. In this project $U_A = 0$ will be used.
 
-The limits, and tolerances, for the pulses are summarised in \autoref{tab:verification-list}. The matched loads are to be within 1\% of the nominal value. \cite{iso_7637_2}
+The limits, and tolerances, for the pulses are summarised in \autoref{tab:verification-list}. The matched loads are to be within 1\% of the nominal value.
+
+The instruments used for measuring the pulses must have at least \SI{400}{\mega\hertz}, since pulse 3a and 3b contains frequency components of up to \SI{200}{\mega\hertz}.
 
 \begin{table}[H]
     \caption{These are all of the verifications that needs to be made before each use of the equipment, along with the limits for each case.}
@@ -312,30 +314,15 @@ The limits, and tolerances, for the pulses are summarised in \autoref{tab:verifi
     \label{tab:verification-list}
 \end{table}
 
-
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \section{Resistors at high frequencies}
 \label{sec:theory:resistors_at_high_frequencies}
 
-\todo[Beskriv frekvensbeteende vid låga/höga värden. Som önskat av methods attenuators-kapitlet]
-
-\todo[Ta upp teori kring parasitiska effekter och icke-ideala modeller]
-
-\url{https://www.edn.com/design/components-and-packaging/4423492/Resistors-aren-t-resistors}
-
-\url{https://www.vishay.com/docs/60107/freqresp.pdf}
-
-Källan \cite{vishay_hf_resistor}.
-
-When working with resistors at high frequencies, one must care for the parasitc properties of the resistor.
-
-Chapter 3.1.6 \cite{theCircuitDesignersCompanion}
-
-\autoref{fig:nonIdealResistor}. \cite{theElectricalEngineeringHandbook}
+When working with resistors at high frequencies, one must consider the parasitc properties of the resistor. Vishay presents a model which consists of the resistance $R$, internal inductance $L$, internal capacitance $C$, external lead inductance $L_C$ and external ground capacitance $C_G$. Since the external ground capacitance is very small in comparison to the other parasitics, it has been neglected in this thesis. The model used for the simulations is depicted in \autoref{fig:nonIdealResistor}, with the values $L = \SI{0.1}{\nano\henry}$, $C = \SI{1}{\pico\farad}$ and $L_C = \SI{1}{\nano\henry}$. This is a bit higher than the values in Vishays paper, but those are also for smaller packages. \cite{vishay_hf_resistor} An approximation of the combined inductance of more than \SI{1}{\nano\henry} for the 1206 package is also in line with the values in a technical information note from AVX for capacitors, the package lead inductance should be similar for capacitors and resistors\cite{avx_cap_parasitic}.
 
 \begin{figure}[H]
     \includegraphics[width=0.5\textwidth]{nonIdealResistor}    
-    \caption{At high frequencies a resistors parasitic inductance and capacitance will affect the behavior of the circuit.}
+    \caption{At high frequencies a resistors parasitic inductance and capacitance will affect the behavior of the circuit. This is the model used in this thesis when simulating circuits.}
     \label{fig:nonIdealResistor}
 \end{figure}
 
@@ -371,11 +358,6 @@ Since \autoref{equ:riseComposite} is based on the rise time limitation but the s
 T_{10-90} = \frac{0.338}{F_{ \SI{3}{\deci\bel}}}
 \end{equation}
 
-%%%%%%%%%%%%%%%%%%%
-\subsection{RF Attenuators}
-RF attenuators are characterized by 
-Linearity, tolerances, power, combinations of resistors, impedances \todo[Fyll på]
-
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \section{Analysis}
 The data points from the measurement must be processed and evaluated to determine if the measured pulse is within the specified limits.
@@ -401,7 +383,7 @@ IEEE-488, or GPIB which it is often called, is a parallel bus interface. It is m
 
 %%%%%%%%%%%%%%%%%%%
 \subsection{Tektronix TDS7104 Oscilloscope}
-The oscilloscope that is available is a Tektronix TDS7104, with specifications as seen in \autoref{tab:tds7104}. It has GPIB interface and TekVISA GPIB, an API for sending GPIB commands over ethernet, available for remote control.
+The oscilloscope that is available is a Tektronix TDS7104, with specifications as seen in \autoref{tab:tds7104}. It has GPIB interface and TekVISA GPIB, an API for sending GPIB commands over ethernet, available for remote control. \todo[Lägg till specs eller ta bort helt]
 
 %%%%%%%%%%%%%%%%%%%
 \subsection{xxxxx Isolated differential probe}