|
|
@@ -116,13 +116,16 @@ The voltages used in the calculations are specified in \autoref{tab:dummy_load_w
|
|
|
\todo[input graph of energy]
|
|
|
|
|
|
\subsection{PCB}
|
|
|
-Since the dummy loads consists of many discrete resistors, it was decided to design a PCB to connect them. This also gives good mechanical control of the resistors and the possibility to design for good heat dissipation.
|
|
|
+\label{sec:dummy_load_pcb}
|
|
|
+Since the dummy loads consists of many discrete resistors, it was decided to design a PCB, printed circuit board, to connect them. This also gives good mechanical control of the resistors and the possibility to design for good heat dissipation.
|
|
|
|
|
|
Because of the high voltages present on the board it was decided to keep a minimum of 3mm functional isolation creepage distance between all traces on the board, in line with the EN 60664-1 standard \cite{en_60664_1}. The board was perforated to allow for better air flow past the resistors, improoving the heat dissipation. The mounting holes for the card was placed in a \SI[product-units=single]{105 x 105}{\milli\meter} square, allowing for a \SI{120}{\milli\meter} fan to be mounted on top of the card using mounting hardware.
|
|
|
|
|
|
A two layer board was chosen, and all of the traces were mirrored on both layers to get as much conductive cross sectional area as possible, and thus lowering the resistance and power dissipation in the traces. The PCB was ordered with \SI{60}{\micro\meter} thick copper layer to further extend the cross sectional areas. The width of the traces for the \SI{2}{\ohm} load was chosen as wide as possible without violating the functional isolation distance.
|
|
|
|
|
|
-Both the circuit schematic and layout editing of the board were performed in the free EDA, Electronic Design Automation, tool KiCad. Before ordering the PCB, it was printed in 1:1 scale and attached to a piece of card board. The card board was then populated with the components already at hand to ensure that the footprints are correct and that the placement of the components makes sense and does not collide.
|
|
|
+Both the circuit schematic and layout editing of the board were performed in the free EDA, Electronic Design Automation, tool KiCad\footnote{KiCad EDA \url{http://kicad-pcb.org/}}.
|
|
|
+
|
|
|
+Before ordering the PCB, it was printed in 1:1 scale and attached to a piece of card board. The card board was then populated with the components already at hand to ensure that the footprints are correct and that the placement of the components makes sense and does not collide, see \autoref{fig:dummy_load_card_board}.
|
|
|
|
|
|
\todo[Fin bild på designprocess av PCB, säkerhetsavstånd etc]
|
|
|
|
|
|
@@ -134,14 +137,15 @@ When the dummy loads had been assembled, their resistances were determined using
|
|
|
The chosen implementation requires a fixture that switches and attenuators, which purpose is to switch the pulse to the desired attenuator or to the dummy load. It must be able to handle the momentary pulse energies and voltages and should not distort the pulse.
|
|
|
|
|
|
\subsection{Attenuators}
|
|
|
+\todo[Massa illustrationer i den här delen]
|
|
|
|
|
|
The target attenuation was decided to mimic the commercial attenuators, described in \autoref{theory_pat_attenuators}, where the \SI{50}{\ohm} attenuator has an attenuation of \SI{54.7}{\deci\bel} and the \SI{1000}{\ohm} attenuator has an attenuation of \SI{60.1}{\deci\bel}.
|
|
|
|
|
|
Only Pulse 3a and Pulse 3b were considered when designing these attenuators, since all other test pulses will be coupled to the separate dummy load.
|
|
|
|
|
|
-The two attenuators were implemented as $\Pi$-attenuators. The values for the attenuators were retrieved from an online calculator\footnote{\url{https://chemandy.com/calculators/matching-pi-attenuator-calculator.htm}}, and then they were simulated in LTSpice to verify the values.
|
|
|
+The two attenuators were implemented as $\Pi$-attenuators. The values for the attenuators were retrieved from an online calculator\footnote{$\Pi$ attenuator calculator \url{https://chemandy.com/calculators/matching-pi-attenuator-calculator.htm}}, and then they were simulated in LTSpice to verify the values.
|
|
|
|
|
|
-By dividing the attenuators into two $\Pi$-networks, the series resistance required will get a bit lower compared to realising them in a single $\Pi$-link. This is desirable because the parasitic capacitance, which is dependant of the resistor package and not the resistance, will influence a high value resistor at lower frequencies that it would on a low value resistor, as explained in \autoref{theory_parasitic_properties}.
|
|
|
+By dividing the attenuators into two $\Pi$-networks, the series resistance required will get a bit lower compared to realizing them in a single $\Pi$-link. This is desirable because the parasitic capacitance, which is dependent of the resistor package and not the resistance, will influence a high value resistor at lower frequencies that it would on a low value resistor, as explained in \autoref{theory_parasitic_properties}.
|
|
|
|
|
|
A resistor with high pulse power and high voltage properties had to be chosen.
|
|
|
|
|
|
@@ -154,8 +158,27 @@ When the number of resistors and its constellations was decided, all of the disc
|
|
|
\subsection{PCB}
|
|
|
\todo[Fin bild på designprocess av PVB, säkerhetsavstånd etc]
|
|
|
|
|
|
-\subsection{Measurement}
|
|
|
+Since the attenuators consits of SMD, surface-mount device, resistors, it was decided to design a PCB for this purpose. This also gives good control of the lengths of the conductors, which is of importance when designing for higher frequencies.
|
|
|
+
|
|
|
+First, the circuit is drawn in the schematic part of the EDA tool KiCad\footnote{KiCad EDA \url{http://kicad-pcb.org/}}. When this is done, the schematic is exported to the PCB layout.
|
|
|
+
|
|
|
+The measurement connectors that will be accessible on the outside of the encapsulation must safe at all times. This involves keeping a minimum creepage distance of \SI{6}{\milli\meter} to any trace that carry a high voltage, according to the regulations in \mbox{EN 60664-1} \cite{en_60664_1}. The EDA tool has functionality for design rule checking, DRC, but there are some limitations in this function that inhibit its use for this case. The DRC in KiCad only allows to set the clearance for a specified net to all other nets. In this case it is only desired to restrict the clearance between the high voltage traces to the traces that are to be considered safe. It is allowed for one high voltage trace to be close to another high voltage trace, only the functional isolation of \SI{3}{\milli\meter} applies here, and it is also allowed for the output signal and the output ground to be close to each other. To aid the design process without the DRC, the high voltage traces was placed on the top layer of the PCB, while all signal traces were placed on the bottom layer. To ensure that enough clearance was kept to the relay pad's, the \SI{6}{\milli\meter} clearance was added to the package footprint as a ring on a user layer in the EDA, as seen in \autoref{fig:kicad_footprint}. This is not an enforced rule, but it helps during the manual design process.
|
|
|
+
|
|
|
+To attach the relay card fixture to the \SI{4}{\mm} banana connectors on the CNA~200, three banana plugs was designed to be screwed directly to the PCB. This makes the conductors as short as possible, and also act as mechanical fastening of the PCB to the case.
|
|
|
+
|
|
|
+Before the PCB was sent for manufacturing, it was also printed in 1:1 scale as the dummy load PCB described in \autoref{sec:dummy_load_pcb}. This also helps to ensure the critical positioning of the \SI{4}{\mm} banana connectors that will attach to the test equipment, as seen in \autoref{fig:relay_card_card_board_equipment}.
|
|
|
|
|
|
+\subsection{Measurement}
|
|
|
The stuff and things done when measuring the shitload yo. Also measured at the other point. Using oscilloscope bla. Hah.
|
|
|
|
|
|
-\section{Analysis}
|
|
|
+Since the relay card will be used in measuring pulses with short rise times, it is of importance to know that it does not distorts the signal too much. It is desired to measure the magnitude response in the frequency domain, as well as the test pulse in time domain.
|
|
|
+
|
|
|
+To measure the magnitude response, a so called S21 measurement was performed using the network analyzer ZVL that is introduced in \autoref{sec:rohde_schwarz_zvl}. To be able to connect the network analyzer, a fixture was made to mimic the front panel of the CNA~200 as seen in \autoref{fig:measurement_fixture}. A programmable relay card was used to control the relays during the testing. The setup can be seen in \autoref{fig:relay_card_measurement_s21}. The signal was measured for each output terminal through each of the attenuators to get the magnitude response for the intended use. To see how well the design suppresses unconnected signals, the magnitude response was also measured when the signal was disconnected completely, i.e. all the control relays were open. In addition to this, the magnitude response was also measured with all but the relays on the current terminal closed, to see if there was any overhearing on the circuit board from the other terminals and the traces after the relays. The results were saved both as an image and as raw data in the form of complex numbers in a CSV, coma separated values, file to allow for further analysis and plotting.
|
|
|
+
|
|
|
+To measure the test pulses through the attenuators, the relay card was connected to the CNA~200 and the pulses were measured on the intended connectors using an oscilloscope, as seen in \autref{fig:relay_card_measurement_time}. The results were saved both as an image and as data points in a CVS file, for further analysis.
|
|
|
+
|
|
|
+To have something to compare the results to, the commercial attenuators were also measured in frequency domain with the ZVL and in time domain using the oscilloscope.
|
|
|
+
|
|
|
+\section{Analysis}
|
|
|
+
|
|
|
+Didn't have no time for this. Yet...
|
Jonatan Gezelius