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- update=2019-05-17 17:44:19
- version=1
- last_client=kicad
- [general]
- version=1
- RootSch=
- BoardNm=
- [cvpcb]
- version=1
- NetIExt=net
- [eeschema]
- version=1
- LibDir=
- [eeschema/libraries]
- [schematic_editor]
- version=1
- PageLayoutDescrFile=
- PlotDirectoryName=
- SubpartIdSeparator=0
- SubpartFirstId=65
- NetFmtName=Pcbnew
- SpiceAjustPassiveValues=0
- LabSize=59
- ERC_TestSimilarLabels=1
- [pcbnew]
- version=1
- PageLayoutDescrFile=
- LastNetListRead=relay_card.net
- CopperLayerCount=2
- BoardThickness=1.6
- AllowMicroVias=0
- AllowBlindVias=0
- RequireCourtyardDefinitions=0
- ProhibitOverlappingCourtyards=1
- MinTrackWidth=0.2
- MinViaDiameter=0.4
- MinViaDrill=0.3
- MinMicroViaDiameter=0.2
- MinMicroViaDrill=0.09999999999999999
- MinHoleToHole=0.25
- TrackWidth1=0.25
- TrackWidth2=0.5
- TrackWidth3=1
- TrackWidth4=2
- TrackWidth5=3
- ViaDiameter1=0.8
- ViaDrill1=0.4
- dPairWidth1=0.2
- dPairGap1=0.25
- dPairViaGap1=0.25
- SilkLineWidth=0.15
- SilkTextSizeV=1
- SilkTextSizeH=1
- SilkTextSizeThickness=0.15
- SilkTextItalic=0
- SilkTextUpright=1
- CopperLineWidth=0.2
- CopperTextSizeV=1.5
- CopperTextSizeH=1.5
- CopperTextThickness=0.3
- CopperTextItalic=0
- CopperTextUpright=1
- EdgeCutLineWidth=0.15
- CourtyardLineWidth=0.05
- OthersLineWidth=0.15
- OthersTextSizeV=1
- OthersTextSizeH=1
- OthersTextSizeThickness=0.15
- OthersTextItalic=0
- OthersTextUpright=1
- SolderMaskClearance=0.2
- SolderMaskMinWidth=0
- SolderPasteClearance=0
- SolderPasteRatio=-0
- [pcbnew/Netclasses]
- [pcbnew/Netclasses/1]
- Name=HV
- Clearance=1.5
- TrackWidth=1
- ViaDiameter=0.8
- ViaDrill=0.4
- uViaDiameter=0.3
- uViaDrill=0.1
- dPairWidth=0.2
- dPairGap=0.25
- dPairViaGap=0.25
- [pcbnew/Netclasses/2]
- Name=LV
- Clearance=1.5
- TrackWidth=1
- ViaDiameter=0.8
- ViaDrill=0.4
- uViaDiameter=0.3
- uViaDrill=0.1
- dPairWidth=0.2
- dPairGap=0.25
- dPairViaGap=0.25
- [pcbnew/Netclasses/3]
- Name=MIDV
- Clearance=1.5
- TrackWidth=1
- ViaDiameter=0.8
- ViaDrill=0.4
- uViaDiameter=0.3
- uViaDrill=0.1
- dPairWidth=0.2
- dPairGap=0.25
- dPairViaGap=0.25
- [pcbnew/Netclasses/4]
- Name=double_saftey
- Clearance=1.5
- TrackWidth=0.25
- ViaDiameter=0.8
- ViaDrill=0.4
- uViaDiameter=0.3
- uViaDrill=0.1
- dPairWidth=0.2
- dPairGap=0.25
- dPairViaGap=0.25
- [pcbnew/Netclasses/5]
- Name=signals
- Clearance=0.4
- TrackWidth=0.5
- ViaDiameter=0.8
- ViaDrill=0.4
- uViaDiameter=0.3
- uViaDrill=0.1
- dPairWidth=0.2
- dPairGap=0.25
- dPairViaGap=0.25
|
