Add automated tests to prescaler

uart_module/testbench/generic_prescaler_tb.vhd

@@ -32,6 +32,9 @@ architecture beh of generic_prescaler_tb is
 
 	signal prescaled_clk_en : std_logic;
 	signal prescaled_clk_en2 : std_logic;
+	
+	constant first_prescaler : integer := 257;
+	constant second_prescaler : integer := 2;
 
 	signal running : boolean := true;
 begin
@@ -50,7 +53,7 @@ begin
 			rst => reset,
 			en => enable,
 			load => '1',
-			prescaler_value => to_unsigned(257, 9),
+			prescaler_value => to_unsigned(first_prescaler, 9),
 			en_out => prescaled_clk_en
 		);
 	
@@ -63,7 +66,7 @@ begin
 			rst => reset,
 			en => prescaled_clk_en,
 			load => '1',
-			prescaler_value => to_unsigned(2, 8),
+			prescaler_value => to_unsigned(second_prescaler, 8),
 			en_out => prescaled_clk_en2
 		);
 	
@@ -93,4 +96,11 @@ begin
 		end if;
 	end process;
 
+	process(clock) is
+	begin
+		if rising_edge(clock) 
+			and num_rising_edges > 1 then
+			assert not (num_rising_edges mod first_prescaler = 0 and prescaled_clk_en /= '1') report "First prescaler not working!" severity error;
+		end if;
+	end process;
 end architecture;