Add generic counter. Not working yet

generic_counter/Makefile

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+GHDL = ghdl
+
+VIEWER = gtkwave
+WAVEFILE = simulation/waves.vcd
+
+#TOP_DESIGN = top.vhd # Not used when not synthesizing..
+# Add design files to this row
+DESIGN_FILES = generic_counter.vhd
+
+DESIGN_FILES_DIR = hdl_design
+DESIGN_FILES_FULL_PATH = $(addprefix $(DESIGN_FILES_DIR)/,$(DESIGN_FILES))
+
+WORK_DIR = simulation
+WORK_LIBRARY = work
+GHDL_OPTIONS = --work=$(WORK_LIBRARY) --workdir=$(WORK_DIR)
+
+# Name of the testbench entity to simulate
+TOP_TESTBENCH = tb
+
+# Add all testbench-related files on this row
+TEST_BENCHES = tb.vhd
+
+TEST_BENCHES_DIR = testbench
+TEST_BENCHES_FULL_PATH = $(addprefix $(TEST_BENCHES_DIR)/,$(TEST_BENCHES))
+
+.PHONY: all clean analyze elaborate run view debug
+
+all: analyze elaborate run view
+
+analyze: $(DESIGN_FILES_FULL_PATH) $(TEST_BENCHES_FULL_PATH)
+	$(GHDL) -a $(GHDL_OPTIONS) $(DESIGN_FILES_FULL_PATH) $(TEST_BENCHES_FULL_PATH)
+
+elaborate: analyze
+	$(GHDL) -e $(GHDL_OPTIONS) $(TOP_TESTBENCH)
+
+run: elaborate
+	$(GHDL) -r $(GHDL_OPTIONS) $(TOP_TESTBENCH) --vcd=$(WAVEFILE)
+
+view: run
+	$(VIEWER) $(WAVEFILE)
+
+clean:
+	$(GHDL) --remove $(GHDL_OPTIONS)
+
+debug:
+	echo $(DESIGN_FILES_FULL_PATH)

generic_counter/hdl_design/generic_counter.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity generic_counter is
+  generic (
+    counter_bits : integer := 8
+    );
+  port
+    (
+      clk : in std_logic;
+      res : in std_logic;
+      en  : in std_logic;
+      cnt : out std_logic_vector (counter_bits -1 downto 0)
+      );
+end entity;
+
+architecture beh of generic_counter is
+  signal cnt_next : std_logic_vector (counter_bits -1 downto 0);
+begin
+  cnt <= (others => '0');
+end architecture;

generic_counter/hdl_design/ha.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ha is
+  port
+    (
+      a : in std_logic;
+      b : in std_logic;
+      o : out std_logic;
+      c : out std_logic
+      );
+end entity;
+
+architecture beh of ha is
+begin
+  o <= a xor b;
+  c <= a and b;
+end architecture;

generic_counter/testbench/tb.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb is
+end entity;
+
+architecture beh of tb is
+  component generic_counter is
+    generic (
+      counter_bits : integer
+      );
+      port
+      (
+        clk : in std_logic;
+        res : in std_logic;
+        en  : in std_logic;
+        cnt : out std_logic_vector (counter_bits -1 downto 0)
+        );
+  end component;
+
+  signal clock, enable_counter, reset : std_logic;
+
+  signal counter_value : std_logic_vector(7 downto 0)
+begin
+
+  --ha_instance : ha port map (q => a, w => b, e => o, r => c);
+  --ha_instance : ha port map (a => q, b => w, o => e, c => r);
+  --ha_instance : ha port map (q, w, e, r);
+  cnt_i1 :
+    generic map(
+      counter_bits => 8
+      )
+      port map(
+        clk => clock,
+        rst => reset,
+        en => enable_counter,
+        cnt => counter_value
+        );
+
+  process is
+  begin
+    clk <= not clk;
+    wait for 10 ns;
+    
+    assert false report "end of simulation";
+    
+    wait;
+  end process;
+
+  process is
+  begin
+    report "Shit!";
+    wait until r = '1';
+    report "It happened!";
+
+    for i in 3 to 6 loop
+      report "Currently at " & integer'image(i);
+      wait for 1 ns;
+    end loop;
+
+    report "At end of test process!";
+    wait;
+  end process;
+
+  -- Invalid report in concurrent statement
+  --report "when is this?";
+  
+end architecture;