Add even more initialization values. Still metavalues detected during simulation..

uart_module/hdl_design/generic_counter.vhd

@@ -16,7 +16,7 @@ entity generic_counter is
 end entity;
 
 architecture beh of generic_counter is
-	signal i_cnt : unsigned (counter_bits -1 downto 0);
+	signal i_cnt : unsigned (counter_bits -1 downto 0) := (others => '0');
 	signal i_cnt_next : unsigned (counter_bits -1 downto 0);
 begin
 	cnt <= i_cnt;

uart_module/hdl_design/generic_prescaler.vhd

@@ -34,13 +34,13 @@ architecture beh of generic_prescaler is
 	signal i_counter_val : unsigned (prescaler_bits -1 downto 0);
 	
 	signal i_match : std_logic;
-	signal i_match_sync : std_logic;
+	signal i_match_sync : std_logic := '0';
 	signal i_reset_counter : std_logic;
 	
 	-- Signals for the edge detector and output
-	signal i_match_last : std_logic;
+	signal i_match_last : std_logic := '0';
 	signal i_en_out : std_logic;
-	signal i_en_out_sync : std_logic;
+	signal i_en_out_sync : std_logic := '0';
 	
 begin
 	en_out <= i_en_out;