Update counter test bench to contain automated testing and nicer clock

uart_module/testbench/generic_counter_tb.vhd

@@ -8,7 +8,7 @@ end entity;
 architecture beh of generic_counter_tb is
 	component generic_counter is
 		generic (
-			counter_bits : integer := 8
+			counter_bits : integer
 		);
 		port(
 			clk : in std_logic;
@@ -17,25 +17,42 @@ architecture beh of generic_counter_tb is
 			cnt : out unsigned (counter_bits -1 downto 0)
 		);
 	end component;
+	
+	constant freq : integer := 50; -- MHz
+	constant period : time := 1000 / freq * 1 ns;
+	constant half_period : time := period / 2;
+	signal num_rising_edges : integer := 0;
 
 	signal clock : std_logic := '0';
-	signal enable_counter : std_logic;
+	signal enable : std_logic;
 	signal reset : std_logic;
 
 	signal counter_value : unsigned(7 downto 0);
 
 	signal running : boolean := true;
 begin
-	running <= true, false after 400 us;
+	running <= true, false after 30 * period;
 	
-	reset <= '0', '1' after 20 us, '0' after 40 us, '1' after 300 us, '0' after 320 us;
+	reset <= '0', '1' after 2 * period, '0' after 3 * period;
 	
-	enable_counter <= '0', '1' after 60 us, '0' after 200 us, '1' after 240 us;
+	enable <= '0', '1' after 5 * period;
 	
+	cnt_i1 : generic_counter
+		generic map(
+			counter_bits => 8
+		)
+		port map(
+			clk => clock,
+			rst => reset,
+			en => enable,
+			cnt => counter_value
+		);
+
+	-- clock process
 	process is
 	begin
 		if running then
-			wait for 10 us;
+			wait for half_period;
 			clock <= not clock;
 		else
 			report "End of simulation!";
@@ -43,15 +60,25 @@ begin
 		end if;
 	end process;
 
-	cnt_i1 : generic_counter
-		generic map(
-			counter_bits => 8
-		)
-		port map(
-			clk => clock,
-			rst => reset,
-			en => enable_counter,
-			cnt => counter_value(1 downto 0)
-		);
+	process(clock) is
+	begin
+		if rising_edge(clock) then
+			if reset = '1' then
+				num_rising_edges <= 0;
+			elsif enable = '1' then
+				num_rising_edges <= num_rising_edges+1;
+			else
+				-- Explicit no change
+				num_rising_edges <= num_rising_edges;
+			end if;
+		end if;
+	end process;
 
+	-- Automated checks
+	process(clock) is
+	begin
+		if rising_edge(clock) then
+			assert num_rising_edges = to_integer(counter_value) report "Counter not working! " & integer'image(to_integer(counter_value)) & " != " & integer'image(num_rising_edges) severity error;
+		end if;
+	end process;
 end architecture;