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@@ -9,7 +9,7 @@ end entity;
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architecture beh of async_8n1_tx_tb is
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architecture beh of async_8n1_tx_tb is
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component generic_prescaler is
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component generic_prescaler is
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generic (
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generic (
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- prescaler_bits : integer := 8
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+ prescaler_bits : integer := 13
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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@@ -51,6 +51,8 @@ architecture beh of async_8n1_tx_tb is
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constant period : time := 1000 / freq * 1 ns;
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constant period : time := 1000 / freq * 1 ns;
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constant half_period : time := period / 2;
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constant half_period : time := period / 2;
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signal num_rising_edges : integer := 0;
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signal num_rising_edges : integer := 0;
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+
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+ constant simulation_periods : integer := 5155*21;
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signal clock : std_logic := '0';
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signal clock : std_logic := '0';
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signal enable : std_logic;
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signal enable : std_logic;
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@@ -58,7 +60,7 @@ architecture beh of async_8n1_tx_tb is
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signal prescaled_clk_en : std_logic;
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signal prescaled_clk_en : std_logic;
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- constant prescaler_value : integer := 5;
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+ constant prescaler_value : integer := 5154;
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constant prescaler_num_bits : integer := integer(ceil(log2(real(prescaler_value))));
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constant prescaler_num_bits : integer := integer(ceil(log2(real(prescaler_value))));
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signal running : boolean := true;
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signal running : boolean := true;
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@@ -75,7 +77,7 @@ architecture beh of async_8n1_tx_tb is
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begin
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begin
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running <= true,
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running <= true,
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- false after 500 * period;
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+ false after simulation_periods * period;
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reset <= '0',
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reset <= '0',
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'1' after 2 * period,
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'1' after 2 * period,
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@@ -112,7 +114,7 @@ begin
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port map(
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port map(
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clk => clock,
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clk => clock,
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rst => reset,
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rst => reset,
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- en => '1', --prescaled_clk_en,
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+ en => prescaled_clk_en,
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wr => wr,
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wr => wr,
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data_in => tx_char,
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data_in => tx_char,
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rdy => rdy1,
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rdy => rdy1,
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@@ -123,7 +125,7 @@ begin
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port map(
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port map(
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clk => clock,
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clk => clock,
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rst => reset,
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rst => reset,
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- en => '1', --prescaled_clk_en,
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+ en => prescaled_clk_en,
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wr => wr,
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wr => wr,
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data_in => tx_char,
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data_in => tx_char,
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rdy => rdy2,
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rdy => rdy2,
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