Working example. Add TCL-script to ease the use of gtkwave

generic_counter/Makefile

@@ -2,10 +2,12 @@ GHDL = ghdl
 
 VIEWER = gtkwave
 WAVEFILE = simulation/waves.vcd
+VIEWERTCL = simulation/gtkwave.tcl
 
 #TOP_DESIGN = top.vhd # Not used when not synthesizing..
+
 # Add design files to this row
-DESIGN_FILES = generic_counter.vhd
+DESIGN_FILES = generic_counter.vhd ha.vhd
 
 DESIGN_FILES_DIR = hdl_design
 DESIGN_FILES_FULL_PATH = $(addprefix $(DESIGN_FILES_DIR)/,$(DESIGN_FILES))
@@ -37,7 +39,7 @@ run: elaborate
 	$(GHDL) -r $(GHDL_OPTIONS) $(TOP_TESTBENCH) --vcd=$(WAVEFILE)
 
 view: run
-	$(VIEWER) $(WAVEFILE)
+	$(VIEWER) $(WAVEFILE) -S $(VIEWERTCL)
 
 clean:
 	$(GHDL) --remove $(GHDL_OPTIONS)

generic_counter/hdl_design/generic_counter.vhd

@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity generic_counter is
   generic (
@@ -8,14 +9,26 @@ entity generic_counter is
   port
     (
       clk : in std_logic;
-      res : in std_logic;
+      rst : in std_logic;
       en  : in std_logic;
-      cnt : out std_logic_vector (counter_bits -1 downto 0)
+      cnt : out unsigned (counter_bits -1 downto 0)
       );
 end entity;
 
 architecture beh of generic_counter is
-  signal cnt_next : std_logic_vector (counter_bits -1 downto 0);
+	signal i_cnt : unsigned (counter_bits -1 downto 0);
+	signal i_cnt_next : unsigned (counter_bits -1 downto 0);
 begin
-  cnt <= (others => '0');
+	cnt <= i_cnt;
+	i_cnt_next <= i_cnt + 1 when rst = '0'
+				else (others => '0');
+
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if en = '1' or rst = '1' then
+				i_cnt <= i_cnt_next;
+			end if;
+		end if;
+	end process;
 end architecture;

generic_counter/simulation/gtkwave.tcl

@@ -0,0 +1,17 @@
+# Add all signals from the top level of test bench
+# i.e. only containing one . character
+set nfacs [ gtkwave::getNumFacs ]
+set all_facs [list]
+for {set i 0} {$i < $nfacs } {incr i} {
+    set facname [ gtkwave::getFacName $i ]
+	set matches [regexp -all {\.} $facname]
+	if {$matches == 1} {
+		lappend all_facs "$facname"
+		puts "Added signal: $facname"
+	}
+}
+set num_added [ gtkwave::addSignalsFromList $all_facs ]
+puts "num signals added: $num_added"
+
+# zoom full
+gtkwave::/Time/Zoom/Zoom_Full

generic_counter/testbench/tb.vhd

@@ -1,68 +1,57 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity tb is
 end entity;
 
 architecture beh of tb is
-  component generic_counter is
-    generic (
-      counter_bits : integer
-      );
-      port
-      (
-        clk : in std_logic;
-        res : in std_logic;
-        en  : in std_logic;
-        cnt : out std_logic_vector (counter_bits -1 downto 0)
-        );
-  end component;
-
-  signal clock, enable_counter, reset : std_logic;
-
-  signal counter_value : std_logic_vector(7 downto 0)
+	component generic_counter is
+		generic (
+			counter_bits : integer
+		);
+		port(
+			clk : in std_logic;
+			rst : in std_logic;
+			en  : in std_logic;
+			cnt : out unsigned (counter_bits -1 downto 0)
+		);
+	end component;
+
+	signal clock : std_logic := '0';
+	signal enable_counter : std_logic;
+	signal reset : std_logic;
+
+	signal counter_value : unsigned(7 downto 0);
+
+	signal running : boolean := true;
 begin
+	running <= true, false after 400 us;
+	
+	reset <= '0', '1' after 20 us, '0' after 40 us, '1' after 300 us, '0' after 320 us;
+	
+	enable_counter <= '0', '1' after 60 us, '0' after 200 us, '1' after 240 us;
+	
+	process is
+	begin
+		if running then
+			wait for 10 us;
+			clock <= not clock;
+		else
+			report "End of simulation!";
+			wait;
+		end if;
+	end process;
+
+	cnt_i1 : generic_counter
+		generic map(
+			counter_bits => 8
+		)
+		port map(
+			clk => clock,
+			rst => reset,
+			en => enable_counter,
+			cnt => counter_value
+		);
 
-  --ha_instance : ha port map (q => a, w => b, e => o, r => c);
-  --ha_instance : ha port map (a => q, b => w, o => e, c => r);
-  --ha_instance : ha port map (q, w, e, r);
-  cnt_i1 :
-    generic map(
-      counter_bits => 8
-      )
-      port map(
-        clk => clock,
-        rst => reset,
-        en => enable_counter,
-        cnt => counter_value
-        );
-
-  process is
-  begin
-    clk <= not clk;
-    wait for 10 ns;
-    
-    assert false report "end of simulation";
-    
-    wait;
-  end process;
-
-  process is
-  begin
-    report "Shit!";
-    wait until r = '1';
-    report "It happened!";
-
-    for i in 3 to 6 loop
-      report "Currently at " & integer'image(i);
-      wait for 1 ns;
-    end loop;
-
-    report "At end of test process!";
-    wait;
-  end process;
-
-  -- Invalid report in concurrent statement
-  --report "when is this?";
-  
 end architecture;