Fix problem with two consecutive sends not loading new data

uart_module/hdl_design/async_8n1_tx.vhd

@@ -115,7 +115,7 @@ begin
 				i_data_reg <= (others => '0');
 			elsif en = '1' and i_current_state = send_data then
 				i_data_reg <= '1' & i_data_reg(7 downto 1);
-			elsif en = '1' and i_current_state = idle and wr = '1' then
+			elsif en = '1' and wr = '1' and (i_current_state = idle or i_current_state = send_stop) then
 				i_data_reg <= data_in;
 			else
 				i_data_reg <= i_data_reg;

uart_module/testbench/async_8n1_tx_tb.vhd

@@ -57,7 +57,7 @@ architecture beh of async_8n1_tx_tb is
 	
 begin
 	running <= true,
-			   false after 50 * period;
+			   false after 500 * period;
 	
 	reset <= '0',
 			 '1' after 2 * period,
@@ -90,7 +90,7 @@ begin
 		port map(
 			clk => clock,
 			rst => reset,
-			en => enable,
+			en => prescaled_clk_en,
 			wr => wr,
 			data_in => tx_char,
 			rdy => rdy,