Style fix

uart_module/testbench/generic_prescaler_tb.vhd

@@ -10,8 +10,7 @@ architecture beh of generic_prescaler_tb is
 		generic (
 			prescaler_bits : integer := 8
 		);
-		port
-		(
+		port(
 			clk : in std_logic;
 			rst : in std_logic;
 			en  : in std_logic;
@@ -70,6 +69,7 @@ begin
 			en_out => prescaled_clk_en2
 		);
 	
+	-- clock process
 	process is
 	begin
 		if running then
@@ -96,6 +96,7 @@ begin
 		end if;
 	end process;
 
+	-- Automated checks
 	process(clock) is
 	begin
 		if rising_edge(clock)