Remove output synchronisation from generic prescaler

uart_module/hdl_design/generic_prescaler.vhd

@@ -45,6 +45,9 @@ architecture beh of generic_prescaler is
 begin
 	en_out <= i_en_out;
 	
+	-- unbuffered match register
+	i_match_reg <= prescaler_value - 1;
+	
 	i_match <= '1' when i_match_reg = i_counter_val
 				else '0';
 				
@@ -70,9 +73,6 @@ begin
 			if rst = '1' then
 				i_match_last <= '0';
 				i_en_out_sync <= '0';
-				if load = '1' then
-					i_match_reg <= prescaler_value - 1;
-				end if;
 			else
 				i_match_last <= i_match_sync;
 				i_en_out_sync <= i_en_out;
@@ -80,12 +80,17 @@ begin
 		end if;
 	end process;
 	
-	-- Output sync
+	-- Sync registers
 	process(clk) is
 	begin
 		if rising_edge(clk) then
 			if rst = '1' then
 				i_match_sync <= '0';
+				
+				-- Buffered match register
+--				if load = '1' then
+--					i_match_reg <= prescaler_value - 1;
+--				end if;
 			elsif en = '1' then
 				i_match_sync <= i_match;
 			end if;