First commit. Makefile seemingly working.

.gitignore

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+*~
+simulation/

Makefile

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+GHDL = ghdl
+
+VIEWER = gtkwave
+WAVEFILE = simulation/waves.vcd
+
+TOP_DESIGN = ha
+DESIGN_FILES_DIR = hdl_design
+DESIGN_FILES = ha.vhd
+DESIGN_FILES_FULL_PATH = $(addprefix $(DESIGN_FILES_DIR)/,$(DESIGN_FILES))
+
+WORK_DIR = simulation
+WORK_LIBRARY = work
+GHDL_OPTIONS = --work=$(WORK_LIBRARY) --workdir=$(WORK_DIR)
+
+TOP_TESTBENCH = ha_tb
+TEST_BENCHES_DIR = testbench
+TEST_BENCHES = ha_tb.vhd
+TEST_BENCHES_FULL_PATH = $(addprefix $(TEST_BENCHES_DIR)/,$(TEST_BENCHES))
+
+.PHONY: all clean analyze elaborate run view debug
+
+all: analyze elaborate run view
+
+analyze: $(DESIGN_FILES_FULL_PATH) $(TEST_BENCHES_FULL_PATH)
+	$(GHDL) -a $(GHDL_OPTIONS) $(DESIGN_FILES_FULL_PATH) $(TEST_BENCHES_FULL_PATH)
+
+elaborate: analyze
+	$(GHDL) -e $(GHDL_OPTIONS) $(TOP_TESTBENCH)
+
+run: elaborate
+	$(GHDL) -r $(GHDL_OPTIONS) $(TOP_TESTBENCH) --vcd=$(WAVEFILE)
+
+view: run
+	$(VIEWER) $(WAVEFILE)
+
+clean:
+	$(GHDL) --remove $(GHDL_OPTIONS)
+
+debug:
+	echo $(DESIGN_FILES_FULL_PATH)

hdl_design/ha.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ha is
+  port
+    (
+      a : in std_logic;
+      b : in std_logic;
+      o : out std_logic;
+      c : out std_logic
+      );
+end entity;
+
+architecture beh of ha is
+begin
+  o <= a xor b;
+  c <= a and b;
+end architecture;

testbench/ha_tb.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ha_tb is
+end entity;
+
+architecture beh of ha_tb is
+  component ha
+    port
+    (
+      a : in std_logic;
+      b : in std_logic;
+      o : out std_logic;
+      c : out std_logic
+      );
+  end component;
+
+  signal q, w, e, r : std_logic;
+begin
+
+  --ha_instance : ha port map (q => a, w => b, e => o, r => c);
+  ha_instance : ha port map (q, w, e, r);
+
+  process is
+  begin
+    
+    q <= 'X';
+    w <= 'X';
+    wait for 5 ns;
+
+    q <= '0';
+    w <= '0';
+    wait for 5 ns;
+
+    q <= '0';
+    w <= '1';
+    wait for 5 ns;
+
+    q <= '1';
+    w <= '0';
+    wait for 5 ns;
+
+    q <= '1';
+    w <= '1';
+    wait for 5 ns;
+
+    assert false report "end of simulation";
+    
+    wait;
+  end process;
+  
+  
+end architecture;