Add initial values in hope of fixing warnings during simulations. Does not seem to work though.

uart_module/hdl_design/async_8n1_tx.vhd

@@ -32,8 +32,8 @@ architecture beh of async_8n1_tx is
 
 	signal i_data_out : std_logic;
 	signal i_rdy : std_logic;
-	signal i_data_reg : unsigned(7 downto 0);
-	signal i_current_state : t_tx_state;
+	signal i_data_reg : unsigned(7 downto 0) := (others => '0');
+	signal i_current_state : t_tx_state := idle;
 	signal i_next_state : t_tx_state;
 	signal i_cnt : unsigned(3 downto 0);
 	signal i_clear_counter : std_logic;

uart_module/hdl_design/async_8n1_tx_v2.vhd

@@ -28,8 +28,8 @@ architecture beh of async_8n1_tx_v2 is
 		);
 	end component;
 
-	signal i_rdy : std_logic;
-	signal i_data_reg : unsigned(8 downto 0);
+	signal i_rdy : std_logic := '1';
+	signal i_data_reg : unsigned(8 downto 0) := (others => '1');
 	signal i_cnt : unsigned(3 downto 0);
 	signal i_clear_counter : std_logic;