library ieee;
use ieee.std_logic_1164.all;

entity generic_counter is
  generic (
    counter_bits : integer := 8
    );
  port
    (
      clk : in std_logic;
      res : in std_logic;
      en  : in std_logic;
      cnt : out std_logic_vector (counter_bits -1 downto 0)
      );
end entity;

architecture beh of generic_counter is
  signal cnt_next : std_logic_vector (counter_bits -1 downto 0);
begin
  cnt <= (others => '0');
end architecture;