library ieee;
use ieee.std_logic_1164.all;

entity tb is
end entity;

architecture beh of tb is
  component generic_counter is
    generic (
      counter_bits : integer
      );
      port
      (
        clk : in std_logic;
        res : in std_logic;
        en  : in std_logic;
        cnt : out std_logic_vector (counter_bits -1 downto 0)
        );
  end component;

  signal clock, enable_counter, reset : std_logic;

  signal counter_value : std_logic_vector(7 downto 0)
begin

  --ha_instance : ha port map (q => a, w => b, e => o, r => c);
  --ha_instance : ha port map (a => q, b => w, o => e, c => r);
  --ha_instance : ha port map (q, w, e, r);
  cnt_i1 :
    generic map(
      counter_bits => 8
      )
      port map(
        clk => clock,
        rst => reset,
        en => enable_counter,
        cnt => counter_value
        );

  process is
  begin
    clk <= not clk;
    wait for 10 ns;
    
    assert false report "end of simulation";
    
    wait;
  end process;

  process is
  begin
    report "Shit!";
    wait until r = '1';
    report "It happened!";

    for i in 3 to 6 loop
      report "Currently at " & integer'image(i);
      wait for 1 ns;
    end loop;

    report "At end of test process!";
    wait;
  end process;

  -- Invalid report in concurrent statement
  --report "when is this?";
  
end architecture;