library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_counter is
  generic (
    counter_bits : integer := 8
    );
  port
    (
      clk : in std_logic;
      rst : in std_logic;
      en  : in std_logic;
      cnt : out unsigned (counter_bits -1 downto 0)
      );
end entity;

architecture beh of generic_counter is
	signal i_cnt : unsigned (counter_bits -1 downto 0) := (others => '0');
	signal i_cnt_next : unsigned (counter_bits -1 downto 0);
begin
	cnt <= i_cnt;
	i_cnt_next <= i_cnt + 1 when rst = '0'
				else (others => '0');

	process(clk) is
	begin
		if rising_edge(clk) then
			if en = '1' or rst = '1' then
				i_cnt <= i_cnt_next;
			end if;
		end if;
	end process;
end architecture;