learning_ghdl/uart_module/testbench/generic_counter_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_counter_tb is
end entity;

architecture beh of generic_counter_tb is
	component generic_counter is
		generic (
			counter_bits : integer := 8
		);
		port(
			clk : in std_logic;
			rst : in std_logic;
			en  : in std_logic;
			cnt : out unsigned (counter_bits -1 downto 0)
		);
	end component;

	signal clock : std_logic := '0';
	signal enable_counter : std_logic;
	signal reset : std_logic;

	signal counter_value : unsigned(7 downto 0);

	signal running : boolean := true;
begin
	running <= true, false after 400 us;
	
	reset <= '0', '1' after 20 us, '0' after 40 us, '1' after 300 us, '0' after 320 us;
	
	enable_counter <= '0', '1' after 60 us, '0' after 200 us, '1' after 240 us;
	
	process is
	begin
		if running then
			wait for 10 us;
			clock <= not clock;
		else
			report "End of simulation!";
			wait;
		end if;
	end process;

	cnt_i1 : generic_counter
		generic map(
			counter_bits => 8
		)
		port map(
			clk => clock,
			rst => reset,
			en => enable_counter,
			cnt => counter_value(1 downto 0)
		);

end architecture;