learning_ghdl/uart_module/hdl_design/generic_prescaler.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_prescaler is
	generic (
		prescaler_bits : integer := 8
	);
	port
	(
		clk : in std_logic;
		rst : in std_logic;
		en  : in std_logic;
		load : in std_logic;
		prescaler_value : in unsigned (prescaler_bits - 1 downto 0);
		en_out : out std_logic
	);
end entity;

architecture beh of generic_prescaler is
	component generic_counter is
		generic (
			counter_bits : integer
		);
		port(
			clk : in std_logic;
			rst : in std_logic;
			en  : in std_logic;
			cnt : out unsigned (counter_bits -1 downto 0)
		);
	end component;
	
	signal i_match_reg : unsigned (prescaler_bits -1 downto 0);
	signal i_counter_val : unsigned (prescaler_bits -1 downto 0);
	
	signal i_match : std_logic;
	signal i_match_sync : std_logic;
	signal i_reset_counter : std_logic;
	
	-- Signals for the edge detector and output
	signal i_match_last : std_logic;
	signal i_en_out : std_logic;
	signal i_en_out_sync : std_logic;
	
begin
	en_out <= i_en_out;
	
	i_match <= '1' when i_match_reg = i_counter_val
				else '0';
				
	i_en_out <= i_match_sync and not i_match_last;
	
	i_reset_counter <= (i_match and en) or rst;

	i_cntr : generic_counter
		generic map(
			counter_bits => prescaler_bits
		)
		port map(
			clk => clk,
			rst => i_reset_counter,
			en => en,
			cnt => i_counter_val
		);

	-- Positive edge detector
	process(clk) is
	begin
		if rising_edge(clk) then
			if rst = '1' then
				i_match_last <= '0';
				i_en_out_sync <= '0';
				if load = '1' then
					i_match_reg <= prescaler_value - 1;
				end if;
			else
				i_match_last <= i_match_sync;
				i_en_out_sync <= i_en_out;
			end if;
		end if;
	end process;
	
	-- Output sync
	process(clk) is
	begin
		if rising_edge(clk) then
			if rst = '1' then
				i_match_sync <= '0';
			elsif en = '1' then
				i_match_sync <= i_match;
			end if;
		end if;
	end process;
end architecture;