learning_ghdl/uart_module/testbench/generic_counter_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_counter_tb is
end entity;

architecture beh of generic_counter_tb is
	component generic_counter is
		generic (
			counter_bits : integer
		);
		port(
			clk : in std_logic;
			rst : in std_logic;
			en  : in std_logic;
			cnt : out unsigned (counter_bits -1 downto 0)
		);
	end component;
	
	constant freq : integer := 50; -- MHz
	constant period : time := 1000 / freq * 1 ns;
	constant half_period : time := period / 2;
	signal num_rising_edges : integer := 0;

	signal clock : std_logic := '0';
	signal enable : std_logic;
	signal reset : std_logic;

	constant counter_bits : integer := 8;
	signal counter_value : unsigned(counter_bits-1 downto 0);

	signal running : boolean := true;
begin
	running <= true, false after 500 * period;
	
	reset <= '0',
			 '1' after 2 * period, 
			 '0' after 3 * period,
			 '1' after 70 * period,
			 '0' after 71 * period;
	
	enable <= '0',
			  '1' after 5 * period,
			  '0' after 100 * period,
			  '1' after 110 * period;
	
	cnt_i1 : generic_counter
		generic map(
			counter_bits => counter_bits
		)
		port map(
			clk => clock,
			rst => reset,
			en => enable,
			cnt => counter_value
		);

	-- clock process
	process is
	begin
		if running then
			wait for half_period;
			clock <= not clock;
		else
			report "End of simulation!";
			wait;
		end if;
	end process;

	process(clock) is
	begin
		if rising_edge(clock) then
			if reset = '1' then
				num_rising_edges <= 0;
			elsif enable = '1' then
				num_rising_edges <= num_rising_edges+1;
			else
				-- Explicit no change
				num_rising_edges <= num_rising_edges;
			end if;
		end if;
	end process;

	-- Automated checks
	process(clock) is
	begin
		if rising_edge(clock) then
			assert (num_rising_edges mod 2**counter_bits) = to_integer(counter_value) report "Counter not working! " & integer'image(to_integer(counter_value)) & " != " & integer'image(num_rising_edges) severity error;
		end if;
	end process;
end architecture;