learning_ghdl/uart_module/testbench/generic_prescaler_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity generic_prescaler_tb is
end entity;

architecture beh of generic_prescaler_tb is
	component generic_prescaler is
		generic (
			prescaler_bits : integer := 8
		);
		port
		(
			clk : in std_logic;
			rst : in std_logic;
			en  : in std_logic;
			load : in std_logic;
			prescaler_value : in unsigned (prescaler_bits - 1 downto 0);
			en_out : out std_logic
		);
	end component;
	
	constant freq : integer := 50; -- MHz
	constant period : time := 1000 / freq * 1 ns;
	constant half_period : time := period / 2;
	signal num_rising_edges : integer := 0;

	signal clock : std_logic := '0';
	signal enable : std_logic;
	signal reset : std_logic;

	signal prescaled_clk_en : std_logic;
	signal prescaled_clk_en2 : std_logic;

	signal running : boolean := true;
begin
	running <= true, false after 530 * period;
	
	reset <= '0', '1' after 2 * period, '0' after 3 * period;
	
	enable <= '0', '1' after 5 * period;
	
	DUT : generic_prescaler
		generic map(
			prescaler_bits => 9
		)
		port map(
			clk => clock,
			rst => reset,
			en => enable,
			load => '1',
			prescaler_value => to_unsigned(257, 9),
			en_out => prescaled_clk_en
		);
	
	DUT2 : generic_prescaler
		generic map(
			prescaler_bits => 8
		)
		port map(
			clk => clock,
			rst => reset,
			en => prescaled_clk_en,
			load => '1',
			prescaler_value => to_unsigned(2, 8),
			en_out => prescaled_clk_en2
		);
	
	process is
	begin
		if running then
			wait for half_period;
			clock <= not clock;
		else
			report "End of simulation!";
			wait;
		end if;
	end process;
	
	
	process(clock) is
	begin
		if rising_edge(clock) then
			if reset = '1' then
				num_rising_edges <= 0;
			elsif enable = '1' then
				num_rising_edges <= num_rising_edges+1;
			else
				-- Explicit no change
				num_rising_edges <= num_rising_edges;
			end if;
		end if;
	end process;

end architecture;