learning_ghdl/testbench/ha_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

entity ha_tb is
end entity;

architecture beh of ha_tb is
  component ha
    port
    (
      a : in std_logic;
      b : in std_logic;
      o : out std_logic;
      c : out std_logic
      );
  end component;

  signal q, w, e, r : std_logic;
begin

  --ha_instance : ha port map (q => a, w => b, e => o, r => c);
  ha_instance : ha port map (q, w, e, r);

  process is
  begin
    
    q <= 'X';
    w <= 'X';
    wait for 5 ns;

    q <= '0';
    w <= '0';
    wait for 5 ns;

    q <= '0';
    w <= '1';
    wait for 5 ns;

    q <= '1';
    w <= '0';
    wait for 5 ns;

    q <= '1';
    w <= '1';
    wait for 5 ns;

    assert false report "end of simulation";
    
    wait;
  end process;

  process is
  begin
    report "Shit!";
    wait until r = '1';
    report "It happened!";
    wait;
  end process;
  
end architecture;