Fix counter testbench

uart_module/testbench/generic_counter_tb.vhd

@@ -27,19 +27,27 @@ architecture beh of generic_counter_tb is
 	signal enable : std_logic;
 	signal reset : std_logic;
 
-	signal counter_value : unsigned(7 downto 0);
+	constant counter_bits : integer := 8;
+	signal counter_value : unsigned(counter_bits-1 downto 0);
 
 	signal running : boolean := true;
 begin
-	running <= true, false after 30 * period;
+	running <= true, false after 500 * period;
 	
-	reset <= '0', '1' after 2 * period, '0' after 3 * period;
+	reset <= '0',
+			 '1' after 2 * period, 
+			 '0' after 3 * period,
+			 '1' after 70 * period,
+			 '0' after 71 * period;
 	
-	enable <= '0', '1' after 5 * period;
+	enable <= '0',
+			  '1' after 5 * period,
+			  '0' after 100 * period,
+			  '1' after 110 * period;
 	
 	cnt_i1 : generic_counter
 		generic map(
-			counter_bits => 8
+			counter_bits => counter_bits
 		)
 		port map(
 			clk => clock,
@@ -78,7 +86,7 @@ begin
 	process(clock) is
 	begin
 		if rising_edge(clock) then
-			assert num_rising_edges = to_integer(counter_value) report "Counter not working! " & integer'image(to_integer(counter_value)) & " != " & integer'image(num_rising_edges) severity error;
+			assert (num_rising_edges mod 2**counter_bits) = to_integer(counter_value) report "Counter not working! " & integer'image(to_integer(counter_value)) & " != " & integer'image(num_rising_edges) severity error;
 		end if;
 	end process;
 end architecture;