Begin uart project

generic_counter/Makefile → uart_module/Makefile

@@ -17,10 +17,10 @@ WORK_LIBRARY = work
 GHDL_OPTIONS = --work=$(WORK_LIBRARY) --workdir=$(WORK_DIR)
 
 # Name of the testbench entity to simulate
-TOP_TESTBENCH = tb
+TOP_TESTBENCH = generic_counter_tb
 
 # Add all testbench-related files on this row
-TEST_BENCHES = tb.vhd
+TEST_BENCHES = generic_counter_tb.vhd
 
 TEST_BENCHES_DIR = testbench
 TEST_BENCHES_FULL_PATH = $(addprefix $(TEST_BENCHES_DIR)/,$(TEST_BENCHES))

generic_counter/testbench/tb.vhd → uart_module/testbench/generic_counter_tb.vhd

@@ -2,13 +2,13 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-entity tb is
+entity generic_counter_tb is
 end entity;
 
-architecture beh of tb is
+architecture beh of generic_counter_tb is
 	component generic_counter is
 		generic (
-			counter_bits : integer
+			counter_bits : integer := 8
 		);
 		port(
 			clk : in std_logic;
@@ -51,7 +51,7 @@ begin
 			clk => clock,
 			rst => reset,
 			en => enable_counter,
-			cnt => counter_value
+			cnt => counter_value(1 downto 0)
 		);
 
 end architecture;