utedass/learning_ghdl @ 478128add2f6b3844241070a02a9fe71f865ce46

Jonatan Gezelius 478128add2 Update counter test bench to contain automated testing and nicer clock		пре 4 година
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hdl_design	a172acb121 Remove output synchronisation from generic prescaler	пре 4 година
simulation	3d076c113b Begin uart project	пре 4 година
testbench	478128add2 Update counter test bench to contain automated testing and nicer clock	пре 4 година
Makefile	550cf3b275 generic prescaler seems to be working as desired.	пре 4 година